參數(shù)資料
型號(hào): PIC18F252
廠(chǎng)商: Microchip Technology Inc.
英文描述: 28-Pin 8-Bit Enhanced FLASH Microcontrollers(28腳、8位增強(qiáng)型閃速微控制器,帶10位A/D)
中文描述: 28引腳8位閃存微控制器增強(qiáng)(28腳,8位增強(qiáng)型閃速微控制器,帶10位A / D轉(zhuǎn)換)
文件頁(yè)數(shù): 310/316頁(yè)
文件大?。?/td> 5755K
代理商: PIC18F252
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)第221頁(yè)第222頁(yè)第223頁(yè)第224頁(yè)第225頁(yè)第226頁(yè)第227頁(yè)第228頁(yè)第229頁(yè)第230頁(yè)第231頁(yè)第232頁(yè)第233頁(yè)第234頁(yè)第235頁(yè)第236頁(yè)第237頁(yè)第238頁(yè)第239頁(yè)第240頁(yè)第241頁(yè)第242頁(yè)第243頁(yè)第244頁(yè)第245頁(yè)第246頁(yè)第247頁(yè)第248頁(yè)第249頁(yè)第250頁(yè)第251頁(yè)第252頁(yè)第253頁(yè)第254頁(yè)第255頁(yè)第256頁(yè)第257頁(yè)第258頁(yè)第259頁(yè)第260頁(yè)第261頁(yè)第262頁(yè)第263頁(yè)第264頁(yè)第265頁(yè)第266頁(yè)第267頁(yè)第268頁(yè)第269頁(yè)第270頁(yè)第271頁(yè)第272頁(yè)第273頁(yè)第274頁(yè)第275頁(yè)第276頁(yè)第277頁(yè)第278頁(yè)第279頁(yè)第280頁(yè)第281頁(yè)第282頁(yè)第283頁(yè)第284頁(yè)第285頁(yè)第286頁(yè)第287頁(yè)第288頁(yè)第289頁(yè)第290頁(yè)第291頁(yè)第292頁(yè)第293頁(yè)第294頁(yè)第295頁(yè)第296頁(yè)第297頁(yè)第298頁(yè)第299頁(yè)第300頁(yè)第301頁(yè)第302頁(yè)第303頁(yè)第304頁(yè)第305頁(yè)第306頁(yè)第307頁(yè)第308頁(yè)第309頁(yè)當(dāng)前第310頁(yè)第311頁(yè)第312頁(yè)第313頁(yè)第314頁(yè)第315頁(yè)第316頁(yè)
PIC18FXX2
DS39564A-page 308
Advance Information
2001 Microchip Technology Inc.
Repeat START Condition
.........................................152
Slave Synchronization
..............................................129
Slow Rise Time (MCLR Tied to V
DD
)
.........................33
SPI Mode Timing (Master Mode) SPI Mode
Master Mode Timing Diagram
..........................128
SPI Mode Timing (Slave Mode with CKE = 0)
.........130
SPI Mode Timing (Slave Mode with CKE = 1)
.........130
STOP Condition Receive or Transmit
......................156
Time-out Sequence on POR w/PLL Enabled
(MCLR Tied to V
DD
)
...........................................33
Time-out Sequence on Power-up
(MCLR Not Tied to V
DD
)
Case 1
................................................................32
Case 2
................................................................32
Time-out Sequence on Power-up
(MCLR Tied to V
DD
)
...........................................32
Timing for Transition Between Timer1 and
OSC1 (HS with PLL)
..........................................23
Transition Between Timer1 and
OSC1 (HS, XT, LP)
............................................22
Transition Between Timer1 and
OSC1 (RC, EC)
..................................................23
Transition from OSC1 to Timer1 Oscillator
................22
USART Asynchronous Master Transmission
...........170
USART Asynchronous Reception
............................172
USART Synchronous Reception
..............................175
USART Synchronous Transmission
.........................174
Wake-up from SLEEP via Interrupt
..........................204
Timing Diagrams and Specifications
................................268
A/D Conversion
........................................................285
A/D Conversion Requirements
.................................285
Brown-out Reset (BOR)
...........................................271
Capture/Compare/PWM (CCP)
................................273
Capture/Compare/PWM Requirements
...................273
CLKOUT and I/O
......................................................269
CLKOUT and I/O Requirements
..............................270
Example SPI Master Mode (CKE = 0)
.....................275
Example SPI Master Mode (CKE = 1)
.....................276
Example SPI Mode Requirements
(Master Mode, CKE = 0)
..................................275
Example SPI Mode Requirements
(Master Mode, CKE = 1)
..................................276
Example SPI Mode Requirements
(Slave Mode CKE = 0)
.....................................277
Example SPI Slave Mode (CKE = 0)
.......................277
Example SPI Slave Mode (CKE = 1)
.......................278
Example SPI Slave Mode Requirements
(CKE = 1)
.........................................................278
External Clock (All Modes except PLL)
....................268
External Clock Requirements
...................................268
I
2
C Bus Data
............................................................279
I
2
C Bus Data Requirements (Slave Mode)
..............280
I
2
C Bus START/STOP Bits
......................................279
Master SSP I
2
C Bus Data Requirements
.................282
Master SSP I
2
C Bus START/STOP
Bits Requirements
............................................281
Oscillator Start-up Timer (OST)
...............................270
Parallel Slave Port (PSP)
.........................................274
Parallel Slave Port Requirements
............................274
PLL Clock
.................................................................269
Power-up Timer (PWRT)
..........................................270
RESET
.....................................................................270
RESET, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements
........................................271
Timer0 and Timer1
.................................................. 272
Timer0 and Timer1 External
Clock Requirements
........................................ 272
USART Synchronous Receive
(Master/Slave)
................................................. 283
USART Synchronous Receive
Requirements
.................................................. 283
USART Synchronous Transmission
Requirements
.................................................. 283
USART Synchronous Transmission
(Master/Slave)
................................................. 283
Watchdog Timer (WDT)
........................................... 270
TRISE Register
.................................................................. 95
PSPMODE Bit
.......................................................93
,
98
TSTFSZ
........................................................................... 249
Two-Word Instructions
Example Cases
.......................................................... 41
TXSTA Register
BRGH Bit
................................................................. 166
U
Universal Synchronous Asynchronous Receiver
Transmitter.
See
USART.
USART
............................................................................. 163
Asynchronous Mode
................................................ 169
Associated Registers, Receive
........................ 172
Associated Registers, Transmit
....................... 170
Master Transmission
....................................... 170
Receive Block Diagram
................................... 171
Receiver
.......................................................... 171
Reception
........................................................ 172
Transmit Block Diagram
.................................. 169
Transmitter
....................................................... 169
Baud Rate Generator (BRG)
................................... 166
Associated Registers
....................................... 166
Baud Rate Error, Calculating
........................... 166
Baud Rate Formula
.......................................... 166
Baud Rates, Asynchronous Mode
(BRGH=0)
................................................ 167
Baud Rates, Asynchronous Mode
(BRGH=1)
................................................ 168
High Baud Rate Select (BRGH Bit)
................. 166
Sampling
.......................................................... 166
RCSTA Register
...................................................... 165
Serial Port Enable (SPEN Bit)
................................. 163
Synchronous Master Mode
...................................... 173
Associated Registers, Reception
..................... 175
Associated Registers, Transmit
....................... 173
Reception
........................................................ 175
Timing Diagram, Synchronous Receive
.......... 283
Timing Diagram, Synchronous
Transmission
........................................... 283
Transmission
................................................... 174
Associated Registers
............................... 173
Synchronous Slave Mode
........................................ 176
Associated Registers, Receive
........................ 177
Associated Registers, Transmit
....................... 176
Reception
........................................................ 177
Transmission
................................................... 176
TXSTA Register
....................................................... 164
相關(guān)PDF資料
PDF描述
PIC18F4523 28/40/44-Pin, Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt Technology
PIC18F4553 28/40/44-Pin High-Performance, Enhanced Flash, USB Microcontrollers with 12-Bit A/D and nanoWatt Technology
PIC18F4585-I Enhanced Flash Microcontrollers with ECAN? Technology, 10-Bit A/D and nanoWatt Technology
PIC18F4585-P Enhanced Flash Microcontrollers with ECAN? Technology, 10-Bit A/D and nanoWatt Technology
PIC18F458ELQTP High Performance, 28/40-Pin Enhanced FLASH Microcontrollers with CAN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PIC18F2520-E/ML 功能描述:8位微控制器 -MCU 32KB 3968 RAM 25I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC18F2520-E/SO 功能描述:8位微控制器 -MCU 32KB 3968 RAM 25I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC18F2520-E/SP 功能描述:8位微控制器 -MCU 32KB 3968 RAM 25I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC18F2520-I/ML 功能描述:8位微控制器 -MCU 32kBF 1536RM 25I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線(xiàn)寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
PIC18F2520-I/ML 制造商:Microchip Technology Inc 功能描述:8-Bit Microcontroller IC