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2001 Microchip Technology Inc.
Advance Information
DS39564A-page 303
PIC18FXX2
I
I/O Ports
.............................................................................85
I
2
C (SSP Module)
ACK Pulse
........................................................ 136
,
137
Read/Write Bit Information (R/W Bit)
.......................137
I
2
C Master Mode Reception
.............................................153
I
2
C Mode
Clock Stretching
.......................................................142
I
2
C Mode (SSP Module)
...................................................132
Registers
..................................................................132
I
2
C Module
ACK Pulse
........................................................ 136
,
137
Acknowledge Sequence Timing
...............................156
Baud Rate Generator
...............................................149
Block Diagram
..........................................................132
Baud Rate Generator
.......................................149
BRG Reset due to SDA Collision
.............................159
BRG Timing
.............................................................150
Bus Collision
Acknowledge
....................................................157
Restart Condition
.............................................160
Restart Condition Timing (Case1)
....................160
Restart Condition Timing (Case2)
....................160
START Condition
.............................................158
START Condition Timing
......................... 158
,
159
STOP Condition
...............................................161
STOP Condition Timing (Case1)
.....................161
STOP Condition Timing (Case2)
.....................161
Transmit Timing
...............................................157
Bus Collision and Arbitration
....................................157
Bus Collision timing
..................................................157
Clock Arbitration
.......................................................150
Effects of a RESET
..................................................157
General Call Address Support
.................................146
Master Mode
............................................................147
Operation
.........................................................148
Repeated START Timing
.................................152
Master Mode 7-bit Reception Timing
.......................155
Master Mode START Condition
...............................151
Master Mode Timing (Transmission)
........................154
Master Mode Transmission
......................................153
Master Mode Transmit Sequence
............................148
Multi-Master Mode
...................................................157
Operation
.................................................................136
Read/Write Bit Information (R/W Bit)
............... 136
,
137
Repeat START Condition Timing
.............................152
Serial Clock (RC3/SCK/SCL)
...................................137
Slave Mode
..............................................................136
Addressing
.......................................................136
Reception
.........................................................137
Transmission
....................................................137
Slave Mode Timing (10-bit Reception, SEN = 0)
.....140
Slave Mode Timing (10-bit reception, SEN = 1)
.......145
Slave Mode Timing (10-bit Transmission)
................141
Slave Mode Timing (7-bit Reception, SEN = 0)
.......138
Slave Mode Timing (7-bit reception, SEN = 1)
.........144
Slave Mode Timing (7-bit Transmission)
..................139
SLEEP Operation
.....................................................157
SSPCON1 Register
.................................................134
SSPCON2 Register
.................................................135
SSPSTAT Register
..................................................133
STOP Condition Receive or Transmit Timing
..........156
STOP Condition Timing
...........................................156
Timing Diagram, Data
..............................................279
Timing Diagram, START/STOP Bits
........................279
ICEPIC In-Circuit Emulator
.............................................. 252
ID Locations
..............................................................193
,
208
INCF
................................................................................ 230
INCFSZ
............................................................................ 231
In-Circuit Serial Programming (ICSP)
.......................193
,
208
Indirect Addressing
............................................................ 51
INDF and FSR Registers
........................................... 50
Indirect Addressing Operation
........................................... 51
Indirect File Operand
......................................................... 42
INFSNZ
............................................................................ 231
Instruction Cycle
................................................................ 39
Instruction Flow/Pipelining
................................................. 40
Instruction Format
............................................................ 211
Instruction Set
.................................................................. 209
ADDLW
.................................................................... 215
ADDWF
.................................................................... 215
ADDWFC
................................................................. 216
ANDLW
.................................................................... 216
ANDWF
.................................................................... 217
BC
............................................................................ 217
BCF
......................................................................... 218
BN
............................................................................ 218
BNC
......................................................................... 219
BNN
......................................................................... 219
BNOV
...................................................................... 220
BNZ
......................................................................... 220
BOV
......................................................................... 223
BRA
......................................................................... 221
BSF
.......................................................................... 221
BTFSC
..................................................................... 222
BTFSS
..................................................................... 222
BTG
......................................................................... 223
BZ
............................................................................ 224
CALL
........................................................................ 224
CLRF
....................................................................... 225
CLRWDT
................................................................. 225
COMF
...................................................................... 226
CPFSEQ
.................................................................. 226
CPFSGT
.................................................................. 227
CPFSLT
................................................................... 227
DAW
........................................................................ 228
DCFSNZ
.................................................................. 229
DECF
....................................................................... 228
DECFSZ
.................................................................. 229
GOTO
...................................................................... 230
INCF
........................................................................ 230
INCFSZ
.................................................................... 231
INFSNZ
.................................................................... 231
IORLW
..................................................................... 232
IORWF
..................................................................... 232
LFSR
....................................................................... 233
MOVF
...................................................................... 233
MOVFF
.................................................................... 234
MOVLB
.................................................................... 234
MOVLW
................................................................... 235
MOVWF
................................................................... 235
MULLW
.................................................................... 236
MULWF
.................................................................... 236
NEGF
....................................................................... 237
NOP
......................................................................... 237
POP
......................................................................... 238
PUSH
....................................................................... 238
RCALL
..................................................................... 239
RESET
..................................................................... 239
RETFIE
.................................................................... 240