PIC18FXX2
DS39564A-page 306
Advance Information
2001 Microchip Technology Inc.
Oscillator Start-up Timer (OST)
......................... 26
,
193
Power-up Timer (PWRT)
.................................... 26
,
193
Time-out Sequence
....................................................26
Time-out Sequence on Power-up
........................32
,
33
Timing Diagram
........................................................270
Prescaler, Capture
...........................................................117
Prescaler, Timer0
.............................................................103
Assignment (PSA Bit)
...............................................103
Rate Select (T0PS2:T0PS0 Bits)
.............................103
Switching Between Timer0 and WDT
......................103
Prescaler, Timer1
.............................................................106
Prescaler, Timer2
.............................................................120
PRO MATE II Universal Device Programmer
...................253
Product Identification System
...........................................311
Program Counter
PCl, PCLATH and PCLATU Register
.........................39
PCLATH Register
.......................................................39
Program Memory
Interrupt Vector
..........................................................35
Map and Stack for PIC18F442/242
............................36
Map and Stack for PIC18F452/252
............................36
RESET Vector
............................................................35
Program Verification
.........................................................205
Program Verification and Code Protection
Associated Registers
...............................................205
Programming, Device Instructions
...................................209
PSP.
See
Parallel Slave Port.
Pulse Width Modulation.
See
PWM (CCP Module).
PUSH
...............................................................................238
PWM (CCP Module)
.........................................................120
Associated Registers
...............................................121
Block Diagram
..........................................................120
CCPR1H:CCPR1L Registers
...................................120
Duty Cycle
................................................................120
Example Frequencies/Resolutions
...........................121
Output Diagram
........................................................120
Period
.......................................................................120
Setup for PWM Operation
........................................121
TMR2 to PR2 Match
.........................................109
,
120
Q
Q Clock
............................................................................120
R
RAM.
See
Data Memory.
RC Oscillator
......................................................................18
RCALL
..............................................................................239
RCON Register
..................................................................53
RCSTA Register
SPEN Bit
..................................................................163
Register File
.......................................................................42
Registers
ADCON0 (A/D Control 0)
.........................................179
ADCON1 (A/D Control 1)
.........................................180
CCP1CON and CCP2CON
(Capture/Compare/PWM Control)
....................115
CONFIG1H (Configuration 1 High)
..........................194
CONFIG2H (Configuration 2 High)
..........................196
CONFIG2L (Configuration 2 Low)
............................195
CONFIG3H (Configuration 3 High)
..........................196
CONFIG4L (Configuration 4 Low)
............................197
CONFIG5H (Configuration 5 High)
..........................198
CONFIG5L (Configuration 5 Low)
............................197
CONFIG6H (Configuration 6 High)
..........................199
CONFIG6L (Configuration 6 Low)
............................198
CONFIG7H (Configuration 7 High)
..........................200
CONFIG7L (Configuration 7 Low)
........................... 199
Device ID Register 1
................................................ 200
Device ID Register 2
................................................ 200
EECON1 (Data EEPROM Control 1)
....................57
,
66
Flag
.......................................................................76
,
77
INTCON (Interrupt Control)
........................................ 73
INTCON2 (Interrupt Control 2)
................................... 74
INTCON3 (Interrupt Control 3)
................................... 75
IPR1 (Peripheral Interrupt Priority 1)
......................... 80
IPR2 (Peripheral Interrupt Priority 2)
......................... 81
LVDCON (LVD Control)
........................................... 189
OSCCON Register
..................................................... 21
PIE1 (Peripheral Interrupt Enable 1)
.......................... 78
PIE2 (Peripheral Interrupt Enable 2)
.......................... 79
PIR1 (Peripheral Interrupt Request 1)
....................... 76
PIR2 (Peripheral Interrupt Request 2)
....................... 77
RCON
........................................................................ 82
RCON (Register Control)
........................................... 82
RCON (RESET Control)
............................................ 53
RCSTA (Receive Status and Control)
..................... 165
SSPCON1 (MSSP Control 1)
I
2
C Mode
......................................................... 134
SPI Mode
......................................................... 125
SSPCON2 (MSSP Control 2)
I
2
C Mode
......................................................... 135
SSPSTAT (SSP Status)
I
2
C Mode
......................................................... 133
SPI Mode
......................................................... 124
STATUS
..................................................................... 52
STKPTR (Stack Pointer)
............................................ 38
Summary
..............................................................46
–
48
T0CON (Timer0 Control)
......................................... 101
T1CON (Timer 1 Control)
........................................ 105
T2CON (Timer 2 Control)
........................................ 109
T3CON (Timer3 Control)
......................................... 111
TRISE
........................................................................ 96
TXSTA (Transmit Status and Control)
..................... 164
WDTCON Register
.................................................. 201
RESET
................................................................25
,
193
,
239
Timing Diagram
....................................................... 270
RETFIE
............................................................................ 240
RETLW
............................................................................ 240
RETURN
.......................................................................... 241
Revision History
............................................................... 297
RLCF
............................................................................... 241
RLNCF
............................................................................. 242
RRCF
............................................................................... 242
RRNCF
............................................................................ 243
S
SCI.
See
USART.
SCK
................................................................................. 123
SDI
................................................................................... 123
SDO
................................................................................. 123
Serial Clock, SCK
............................................................ 123
Serial Communication Interface.
See
USART.
Serial Data In, SDI
........................................................... 123
Serial Data Out, SDO
....................................................... 123
Serial Peripheral Interface.
See
SPI.
SETF
................................................................................ 243
Slave Select Synchronization
.......................................... 129
Slave Select, SS
.............................................................. 123
SLEEP
..............................................................193
,
203
,
244
Software Simulator (MPLAB SIM)
.................................... 252
Special Event Trigger.
See
Compare.