參數(shù)資料
型號(hào)： PIC16F877A
廠商： Microchip Technology Inc.
英文描述： 40-Pin 8-Bit Enhanced FLASH Microcontroller(40引腳、8位增強(qiáng)型FLASH微控制器)
中文描述： 40引腳8位閃存微控制器增強(qiáng)（40引腳，8位增強(qiáng)型閃存微控制器）
文件頁(yè)數(shù)： 35/222頁(yè)
文件大?。?/td> 4012K
代理商： PIC16F877A
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2001 Microchip Technology Inc.
Advance Information
DS39582A-page 33
PIC16F87XA
3.3
Reading Data EEPROM Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD con-
trol bit (EECON1<7>), and then set control bit RD
(EECON1<0>). The data is available in the very next
cycle, in the EEDATA register; therefore, it can be read
in the next instruction (see Example 3-1). EEDATA will
hold this value until another read, or until it is written to
by the user (during a write operation).
The steps to reading the EEPROM data memory are:
1.
Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
2.
Clear the EEPGD bit to point to EEPROM data
memory.
3.
Set the RD bit to start the read operation.
4.
Read the data from the EEDATA register.
EXAMPLE 3-1:
DATA EEPROM READ
3.4
Writing to Data EEPROM Memory
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data to
the EEDATA register. Then the user must follow a spe-
cific write sequence to initiate the write for each byte.
The write will not initiate if the write sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment (see Example 3-2).
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt or poll this bit. EEIF must be
cleared by software.
The steps to write to EEPROM data memory are:
1.
If step 10 is not implemented, check the WR bit
to see if a write is in progress.
2.
Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
3.
Write the 8-bit data value to be programmed in
the EEDATA register.
4.
Clear the EEPGD bit to point to EEPROM data
memory.
5.
Set the WREN bit to enable program operations.
6.
Disable interrupts (if enabled).
7.
Execute the special five instruction sequence:
Write 55h to EECON2 in two steps (first to W,
then to EECON2)
Write AAh to EECON2 in two steps (first to W,
then to EECON2)
Set the WR bit
8.
Enable interrupts (if using interrupts).
9.
Clear the WREN bit to disable program
operations.
10. At the completion of the write cycle, the WR bit
is cleared and the EEIF interrupt flag bit is set.
(EEIF must be cleared by firmware.) If step 1 is
not implemented, then firmware should check
for EEIF to be set, or WR to clear, to indicate the
end of the program cycle.
EXAMPLE 3-2:
DATA EEPROM WRITE
BSF
BCF
MOVF
MOVWF
BSF
BCF
STATUS,RP1
STATUS,RP0
DATA_EE_ADDR,W ; Data Memory
EEADR
STATUS,RP0
EECON1,EEPGD
;
; Bank 2
; Address to read
; Bank 3
; Point to Data
; memory
; EE Read
; Bank 2
; W = EEDATA
BSF
BCF
MOVF
EECON1,RD
STATUS,RP0
EEDATA,W
BSF
BSF
BTFSC
GOTO
BCF
MOVF
MOVWF
MOVF
MOVWF
BSF
BCF
STATUS,RP1
STATUS,RP0
EECON,WR1
$-1
STATUS,
DATA_EE_ADDR,W ;Data Memory
EEADR
DATA_EE_DATA,W ;Data Memory Value
EEDATA
;to write
STATUS,RP0
;Bank 3
EECON1,EEPGD
;Point to DATA
;memory
EECON1,WREN
;Enable writes
;
;Wait for write
;to complete
;Bank 2
RP0
;Address to write
BSF
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
;Disable INTs.
;
;Write 55h
;
;Write AAh
;Set WR bit to
;begin write
;Enable INTs.
;Disable writes
BSF
BCF
INTCON,GIE
EECON1,WREN
R
S
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