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參數(shù)資料
| 型號(hào)： | PIC16F877A |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 40-Pin 8-Bit Enhanced FLASH Microcontroller(40引腳、8位增強(qiáng)型FLASH微控制器) |
| 中文描述： | 40引腳8位閃存微控制器增強(qiáng)（40引腳，8位增強(qiáng)型閃存微控制器） |
| 文件頁(yè)數(shù)： | 33/222頁(yè) |
| 文件大?。?/td> | 4012K |
| 代理商： | PIC16F877A |
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2001 Microchip Technology Inc.
Advance Information
DS39582A-page 31
PIC16F87XA
3.0
DATA EEPROM AND
FLASH PROGRAM MEMORY
The Data EEPROM and FLASH Program memory is
readable and writable during normal operation (over
the full V
DD
range). This memory is not directly mapped
in the register file space. Instead, it is indirectly
addressed through the Special Function Registers.
There are six SFRs used to read and write this
memory:
EECON1
EECON2
EEDATA
EEDATH
EEADR
EEADRH
When interfacing to the data memory block, EEDATA
holds the 8-bit data for read/write, and EEADR holds
the address of the EEPROM location being accessed.
These devices have 128 or 256 bytes of data EEPROM
(depending on the device), with an address range from
00h to FFh. On devices with 128 bytes, addresses from
80h to FFh are unimplemented and will wrap around to
the beginning of data EEPROM memory. When writing
to unimplemented locations, the on-chip charge pump
will be turned off.
When interfacing the program memory block, the
EEDATA and EEDATH registers form a two-byte word
that holds the 14-bit data for read/write, and the
EEADR and EEADRH registers form a two-byte word
that holds the 13-bit address of the program memory
location being accessed. These devices have 4 or 8K
words of program FLASH with an address range from
0000h to 0FFFh for the PIC16F873A/874A, and 0000h
to 1FFFh for the PIC16F876A/877A. Addresses above
the range of the respective device will wrap around to
the beginning of program memory.
The EEPROM data memory allows single byte read
and write. The FLASH program memory allows single
word reads and four-word block writes. Program mem-
ory write operations automatically perform an erase-
before-write on blocks of four words. A byte write in
data EEPROM memory automatically erases the loca-
tion and writes the new data (erase before write).
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on chip
charge pump, rated to operate over the voltage range
of the device for byte or word operations.
When the device is code protected, the CPU may
continue to read and write the data EEPROM memory.
Depending on the settings of the write protect bits, the
device may or may not be able to write certain blocks
of the program memory; however, reads of the program
memory are allowed. When code protected, the device
programmer can no longer access data or program
memory; this does NOT inhibit internal reads or writes.
3.1
EEADR and EEADRH
The EEADRH:EEADR register pair can address up to
a maximum of 256 bytes of data EEPROM or up to a
maximum of 8K words of program EEPROM. When
selecting a data address value, only the LSByte of the
address is written to the EEADR register. When select-
ing a program address value, the MSByte of the
address is written to the EEADRH register and the
LSByte is written to the EEADR register.
If the device contains less memory than the full address
reach of the address register pair, the Most Significant
bits of the registers are not implemented. For example,
if the device has 128 bytes of data EEPROM, the Most
Significant bit of EEADR is not implemented on access
to data EEPROM.
3.2
EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
Control bit EEPGD determines if the access will be a
program or data memory access. When clear, as it is
when reset, any subsequent operations will operate on
the data memory. When set, any subsequent opera-
tions will operate on the program memory.
Control bits RD and WR initiate read and write or erase,
respectively. These bits cannot be cleared, only set, in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write or erase
operation. On power-up, the WREN bit is clear. The
WRERR bit is set when a write (or erase) operation is
interrupted by a MCLR or a WDT Time-out Reset dur-
ing normal operation. In these situations, following
RESET, the user can check the WRERR bit and rewrite
the location. The data and address will be unchanged
in the EEDATA and EEADR registers.
Interrupt flag bit EEIF in the PIR2 register is set when
write is complete. It must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all '
0
's. The EECON2 register is used
exclusively in the EEPROM write sequence.
Note:
The self-programming mechanism for
FLASH program memory has been
changed.
On
previous
devices, FLASH programming was done in
single word erase/write cycles. The newer
PIC16F87XA devices use a four-word
erase/write cycle. See Section 3.6 for
more information.
PIC16F87X
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