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| 型號(hào)： | PIC16F877A |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 40-Pin 8-Bit Enhanced FLASH Microcontroller(40引腳、8位增強(qiáng)型FLASH微控制器) |
| 中文描述： | 40引腳8位閃存微控制器增強(qiáng)（40引腳，8位增強(qiáng)型閃存微控制器） |
| 文件頁數(shù)： | 212/222頁 |
| 文件大?。?/td> | 4012K |
| 代理商： | PIC16F877A |
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PIC16F87XA
DS39582A-page 210
Advance Information
2001 Microchip Technology Inc.
Capture/Compare/PWM Requirements
(CCP1 and CCP2)
....................................................184
CCP.
See
Capture/Compare/PWM.
CCP1CON
..........................................................................19
CCP1CON Register
...........................................................17
CCP2CON
..........................................................................19
CCP2CON Register
...........................................................17
CCPR1H Register
.................................................. 17
,
19
,
61
CCPR1L Register
................................................... 17
,
19
,
61
CCPR2H Register
........................................................ 17
,
19
CCPR2L Register
......................................................... 17
,
19
CCPxM0 bit
........................................................................62
CCPxM1 bit
........................................................................62
CCPxM2 bit
........................................................................62
CCPxM3 bit
........................................................................62
CCPxX bit
...........................................................................62
CCPxY bit
...........................................................................62
CLKOUT and I/O Timing Requirements
...........................181
CMCON Register
...............................................................18
Code Examples
Call of a Subroutine in Page 1 from Page 0
...............28
Indirect Addressing
....................................................29
Initializing PORTA
......................................................39
Loading the SSPBUF (SSPSR) Register
...................72
Reading Data EEPROM
.............................................33
Reading FLASH Program Memory
............................34
Saving STATUS, W and PCLATH Registers
...........152
Writing to Data EEPROM
...........................................33
Writing to FLASH Program Memory
...........................36
Code Protection
....................................................... 141
,
155
Comparator Module
.........................................................133
Analog Input Connection Considerations
.................137
Associated Registers
...............................................138
Configuration
............................................................134
Effects of RESET
.....................................................137
Interrupts
..................................................................136
Operation
.................................................................135
Operation During SLEEP
.........................................137
Outputs
.....................................................................135
Reference
.................................................................135
Response Time
........................................................135
Comparator Voltage Reference
.......................................139
Associated Registers
...............................................140
Computed GOTO
...............................................................28
Configuration Bits
.............................................................141
Configuration Word
..........................................................142
Conversion Considerations
..............................................208
CVRCON Register
.............................................................18
D
Data EEPROM and FLASH Program Memory
EEADR Register
........................................................31
EEADRH Register
......................................................31
EECON1 Register
......................................................31
EECON2 Register
......................................................31
EEDATA Register
......................................................31
EEDATH Register
......................................................31
Data EEPROM Memory
Associated Registers
................................................. 37
EEADR Register
........................................................ 31
EEADRH Register
..................................................... 31
EECON1 Register
...................................................... 31
EECON2 Register
...................................................... 31
Operation During Code Protect
................................. 37
Protection Against Spurious Writes
........................... 37
Reading
..................................................................... 33
Write Complete Flag (EEIF Bit)
................................. 31
Writing
........................................................................ 33
Data Memory
..................................................................... 14
Bank Select (RP1:RP0 Bits)
.................................14
,
20
General Purpose Registers
....................................... 14
Register File Map
..................................................15
,
16
Special Function Registers
........................................ 17
DC and AC Characteristics Graphs and Tables
.............. 195
DC Characteristics
....................................................173
–
177
Development Support
...................................................... 165
Device Differences
........................................................... 207
Device Overview
.................................................................. 5
Direct Addressing
............................................................... 29
E
EEADR Register
...........................................................19
,
31
EEADRH Register
.........................................................19
,
31
EECON1 Register
.........................................................19
,
31
EECON2 Register
.........................................................19
,
31
EEDATA Register
.............................................................. 19
EEDATH Register
.............................................................. 19
Electrical Characteristics
.................................................. 171
Errata
................................................................................... 4
External Interrupt Input (RB0/INT).
See
Interrupt Sources.
External Reference Signal
............................................... 135
F
Firmware Instructions
....................................................... 157
FLASH Program Memory
Associated Registers
................................................. 37
EECON1 Register
...................................................... 31
EECON2 Register
...................................................... 31
Reading
..................................................................... 34
Writing
........................................................................ 35
FSR Register
....................................................17
,
18
,
19
,
29
G
General Call Address Support
........................................... 92
I
I/O Ports
............................................................................. 39
I2C Bus Data Requirements
............................................ 190
I
2
C Bus START/STOP Bits Requirements
....................... 189
I2C Mode
Registers
.................................................................... 78
I
2
C Mode
............................................................................ 78
ACK Pulse
............................................................82
,
83
Acknowledge Sequence Timing
.............................. 102
Baud Rate Generator
................................................. 95
Bus Collision
Repeated START Condition
............................ 106
START Condition
............................................. 104
STOP Condition
............................................... 107
Clock Arbitration
........................................................ 96
Effect of a RESET
.................................................... 103
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