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| 型號： | PIC16CR620A |
| 廠商： | Microchip Technology Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | EPROM-Based 8-Bit CMOS Microcontroller |
| 中文描述： | 存儲器為基礎的8位CMOS微控制器 |
| 文件頁數(shù)： | 55/108頁 |
| 文件大?。?/td> | 645K |
| 代理商： | PIC16CR620A |
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1998 Microchip Technology Inc.
Preliminary
DS30235G-page 55
PIC16C62X
9.5
Interrupts
The PIC16C62X has 4 sources of interrupt:
External interrupt RB0/INT
TMR0 overflow interrupt
PortB change interrupts (pins RB7:RB4)
Comparator interrupt
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on reset.
The “return from interrupt” instruction,
RETFIE
, exits
interrupt routine as well as sets the GIE bit, which
re-enable RB0/INT interrupts.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag is contained in the special
register PIR1. The corresponding interrupt enable bit is
contained in special registers PIE1.
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in soft-
ware before re-enabling interrupts to avoid RB0/INT
recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 9-16).
The latency is the same for one or two cycle
instructions. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid multiple interrupt requests. Individual interrupt
flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit.
Note 1:
Individual interrupt flag bits are set
regardless of the status of their
corresponding mask bit or the GIE bit.
When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The CPU will execute a
NOP in the cycle immediately following
the instruction which clears the GIE bit.
The interrupts which were ignored are
still pending to be serviced when the GIE
bit is set again.
2:
FIGURE 9-15: INTERRUPT LOGIC
RBIF
RBIE
T0IF
T0IE
INTF
INTE
GIE
PEIE
Wake-up
(If in SLEEP mode)
Interrupt
to CPU
CMIE
CMIF
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