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| 型號： | PIC16CR620A |
| 廠商： | Microchip Technology Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | EPROM-Based 8-Bit CMOS Microcontroller |
| 中文描述： | 存儲器為基礎(chǔ)的8位CMOS微控制器 |
| 文件頁數(shù)： | 28/108頁 |
| 文件大?。?/td> | 645K |
| 代理商： | PIC16CR620A |
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PIC16C62X
DS30235G-page 28
Preliminary
1998 Microchip Technology Inc.
5.2
PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A '1' in
the TRISB register puts the corresponding output driver
in a high impedance mode. A '0' in the TRISB register
puts the contents of the output latch on the selected
pin(s).
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
Each of the PORTB pins has a weak internal pull-up
(
≈
200
μ
A typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RBIF interrupt (flag
latched in INTCON<0>).
FIGURE 5-5:
BLOCK DIAGRAM OF
RB7:RB4 PINS
Data Latch
D
From other
RB7:RB4 pins
RBPU
(2)
P
V
DD
I/O
pin
(1)
Q
CK
Q
D
CK
Q
D
EN
Q
D
EN
Data bus
WR PortB
WR TRISB
Set RBIF
TRIS Latch
RD TRISB
RD PortB
weak
pull-up
RD Port
Latch
TTL
Input
Buffer
Note 1: I/O pins have diode protection to V
DD
and V
SS
.
Note 2: TRISB = 1 enables weak pull-up if RBPU = '0'
(OPTION<7>).
ST
Buffer
RB7:RB6 in serial programming mode
Q
Q
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a)
Any read or write of PORTB. This will end the
mismatch condition.
b)
Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression. (See AN552 in the
Microchip Embedded Control Handbook)
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-6:
BLOCK DIAGRAM OF
RB3:RB0 PINS
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF inter-
rupt flag may not get set.
Data Latch
D
RBPU
(2)
P
V
DD
Q
CK
D
CK
Q
D
EN
Data bus
WR PortB
WR TRISB
RD TRISB
RD PortB
weak
pull-up
RD Port
RB0/INT
I/O
pin
(1)
TTL
Input
Buffer
Note 1: I/O pins have diode protection to V
DD
and V
SS
.
Note 2: TRISB = 1 enables weak pull-up if RBPU = '0'
(OPTION<7>).
ST
Buffer
Q
Q
Q
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