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參數(shù)資料
| 型號(hào)： | PIC16CR620A |
| 廠商： | Microchip Technology Inc. |
| 元件分類： | 8位微控制器 |
| 英文描述： | EPROM-Based 8-Bit CMOS Microcontroller |
| 中文描述： | 存儲(chǔ)器為基礎(chǔ)的8位CMOS微控制器 |
| 文件頁(yè)數(shù)： | 51/108頁(yè) |
| 文件大小： | 645K |
| 代理商： | PIC16CR620A |
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1998 Microchip Technology Inc.
Preliminary
DS30235G-page 51
PIC16C62X
9.4.5
TIME-OUT SEQUENCE
On power-up the time-out sequence is as follows: First
PWRT time-out is invoked after POR has expired. Then
OST is activated. The total time-out will vary based on
oscillator configuration and PWRTE bit status. For
example, in RC mode with PWRTE bit erased (PWRT
disabled), there will be no time-out at all. Figure 9-9,
Figure 9-10
and
Figure 9-11
sequences.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 9-10). This is useful for testing purposes or
to synchronize more than one PIC16C62X device oper-
ating in parallel.
Table 9-6 shows the reset conditions for some special
registers, while Table 9-7 shows the reset conditions for
all the registers.
depict
time-out
9.4.6
POWER CONTROL (PCON)/
STATUS REGISTER
The power control/status register, PCON (address
8Eh) has two bits.
Bit0 is BOR (Brown-out). BOR is unknown on
power-on-reset. It must then be set by the user and
checked on subsequent resets to see if BOR = 0
indicating that a brown-out has occurred. The BOR
status bit is a don’t care and is not necessarily
predictable if the brown-out circuit is disabled (by
setting BOREN bit = 0 in the Configuration word).
Bit1 is POR (Power-on-reset). It is a ‘0’ on
power-on-reset and unaffected otherwise. The user
must write a ‘1’ to this bit following a power-on-reset.
On a subsequent reset if POR is ‘0’, it will indicate that
a power-on-reset must have occurred (V
DD
may have
gone too low).
TABLE 9-3:
TIME-OUT IN VARIOUS SITUATIONS
TABLE 9-4:
STATUS/PCON BITS AND THEIR SIGNIFICANCE
Legend: u = unchanged, x = unknown
Oscillator Configuration
Power-up
Brown-out Reset
Wake-up
from SLEEP
PWRTE = 0
PWRTE = 1
XT, HS, LP
72 ms + 1024 T
OSC
1024 T
OSC
72 ms + 1024 T
OSC
1024 T
OSC
RC
72 ms
—
72 ms
—
POR
BOR
TO
PD
0
X
1
1
Power-on-reset
0
X
0
X
Illegal, TO is set on POR
0
X
X
0
Illegal, PD is set on POR
1
0
X
X
Brown-out Reset
1
1
0
u
WDT Reset
1
1
0
0
WDT Wake-up
1
1
u
u
MCLR reset during normal operation
1
1
1
0
MCLR reset during SLEEP
TABLE 9-5:
SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on POR
Reset
Value on all
other resets
(1)
83h
8Eh
Note1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during normal operation.
STATUS
PCON
TO
—
PD
—
0001 1xxx
000q quuu
—
—
—
—
POR
BOR
---- --0x
---- --uq
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