1996 Microchip Technology Inc.
Preliminary
DS40122B-page 117
PIC14000
FIGURE 13-7: I2C BUS DATA TIMING
TABLE 13-8: I2C BUS DATA REQUIREMENTS
Parameter
No.
Sym
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock high time
100 kHz mode
4.0
—
s
PIC14000 must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
s
PIC14000 must operate at a
minimum of 10 MHz
I2C Module
1.5 TCY
—
101
TLOW
Clock low time
100 kHz mode
4.7
—
s
PIC14000 must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
s
PIC14000 must operate at a
minimum of 10 MHz
I2C Module
1.5 TCY
—
102
TR
SDA and SCL rise
time
100 kHz mode
—
1000
ns
400 kHz mode
20+0.1 Cb
300
ns
Cb is specied to be from
10-400 pF
103
TF
SDA and SCL fall
time
100 kHz mode
—
300
ns
400 kHz mode
20+0.1 Cb
300
ns
Cb is specied to be from
10-400 pF
90
TSU:STA
START condition
setup time
100 kHz mode
4.7
—
s
Only relevant for repeated
START condition
400 kHz mode
0.6
—
s
91
THD:STA
START condition hold
time
100 kHz mode
4.0
—
s
After this period the rst clock
pulse is generated
400 kHz mode
0.6
—
s
106
THD:DAT
Data input hold time
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
s
107
TSU:DAT
Data input setup time
100 kHz mode
250
—
ns
Note 2
400 kHz mode
100
—
ns
92
TSU:STO
STOP condition setup
time
100 kHz mode
4.7
—
s
400 kHz mode
0.6
—
s
109
TAA
Output valid from
clock
100 kHz mode
—
3500
ns
Note 1
400 kHz mode
—
ns
110
TBUF
Bus free time
100 kHz mode
4.7
—
s
Time the bus must be free
before a new transmission
can start
400 kHz mode
1.3
—
s
Cb
Bus capacitive loading
—
400
pF
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undened region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of STARTs or STOPs.
2: A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement
tSU:DAT
≥250ns must then be met. This will automatically be the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the
next data bit to the SDA line TR max.+tSU:DAT=1000+250=1250 ns (according to the standard-mode I2C
bus specication) before the SCL line is released.
SCL
SDA
IN
SDA
OUT
80
93
90
91
92
82
100
99
81
96
97
90
91
92
100
101
103
106
107
109
110
102