參數(shù)資料
型號: PIC14000-04I/SP
廠商: Microchip Technology
文件頁數(shù): 130/153頁
文件大?。?/td> 0K
描述: IC MCU OTP 4KX14 A/D 28DIP
產品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 15
系列: PIC® 14
核心處理器: PIC
芯體尺寸: 8-位
速度: 4MHz
連通性: I²C
外圍設備: POR,溫度傳感器,WDT
輸入/輸出數(shù): 20
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: OTP
RAM 容量: 192 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 6 V
數(shù)據(jù)轉換器: 斜率 A/D
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
配用: ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
ICE2000-ND - EMULATOR MPLAB-ICE 2000 POD
PIC14000
DS40122B-page 78
Preliminary
1996 Microchip Technology Inc.
Figure 10-6 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a
180-degree phase shift in a series resonant oscillator
circuit. The 330 k
resistors provide the negative
feedback to bias the inverters in their linear region.
FIGURE 10-6: EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
330k
74AS04
PIC14000
OSC1
To Other
Devices
XTAL
330k
74AS04
0.1
F
10.3
Reset
The PIC14000 differentiates between various kinds of
reset:
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset (normal operation)
Some registers are not affected in any reset condition;
their status is unknown on POR and unchanged in any
other reset. Most other registers are reset to a “reset
state” on Power-on Reset (POR), on the MCLR and
WDT Reset, and on MCLR Reset during SLEEP. They
are not affected by a WDT Wake-up, which is viewed
as the resumption of normal operation. The TO and PD
bits are set or cleared differently in different reset situ-
ations as indicated in Table 10-3. These bits are used
in software to determine the nature of the reset. See
Table 10-5 for a full description of reset states of all reg-
isters.
A simplied block diagram of the on-chip reset circuit is
shown in Figure 10-7.
The devices all have a MCLR noise lter in the MCLR
reset path. The lter will detect and ignore small pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
FIGURE 10-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R
Q
External
Reset
MCLR
VDD
OSC1
WDT
Module
VDD rise
detect
OST/PWRT
On-chip(1)
RC OSC
WDT
Time-out
Power-on Reset
OST
10-bit Ripple counter
PWRT
Chip_Reset
10-bit Ripple counter
Enable OST
Enable PWRT
SLEEP
Note
1: This is a separate oscillator from the RC
oscillator of the CLKIN pin.
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