參數(shù)資料
型號： PIC12F683-I/SN
廠商： Microchip Technology
文件頁數(shù)： 33/176頁
文件大小： 0K
描述： IC MCU FLASH 2KX14 8SOIC
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
Digi-Key 應(yīng)用說明： AN0005 PWM Example with Microchip's CCP Module
AN0005 Example Code
標(biāo)準(zhǔn)包裝： 100
系列： PIC® 12F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 5
程序存儲器容量： 3.5KB（2K x 14）
程序存儲器類型： 閃存
EEPROM 大小： 256 x 8
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
包裝： 管件
產(chǎn)品目錄頁面： 645 (CN2011-ZH PDF)
配用： AC162058-ND - HEADER MPLAB ICD2 FOR PIC12F683
I3-DB12F683-ND - BOARD DAUGHTER ICEPIC3
其它名稱： PIC12F683-I/SNG
PIC12F683-I/SNG-ND
PIC12F683
DS41211D-page 126
2007 Microchip Technology Inc.
TABLE 15-2:
OSCILLATOR PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature
-40°C
≤ TA ≤ +125°C
Param
No.
Sym
Characteristic
Freq.
Tolerance
Min
Typ
Max
Units
Conditions
OS06
TWARM
Internal Oscillator Switch
when running(3)
——
—
2
TOSC
Slowest clock
OS07
TSC
Fail-Safe Sample Clock
Period(1)
—
—21
—
ms
LFINTOSC/64
OS08
HFOSC
Internal Calibrated
HFINTOSC Frequency(2)
±1%
7.92
8.0
8.08
MHz
VDD = 3.5V, 25°C
±2%
7.84
8.0
8.16
MHz
2.5V
≤ VDD ≤ 5.5V,
0°C
≤ TA ≤ +85°C
±5%
7.60
8.0
8.40
MHz
2.0V
≤ VDD ≤ 5.5V,
-40°C
≤ TA ≤ +85°C (Ind.),
-40°C
≤ TA ≤ +125°C (Ext.)
OS09*
LFOSC
Internal Uncalibrated
LFINTOSC Frequency
—
153145
kHz
OS10*
TIOSC
ST
HFINTOSC Oscillator
Wake-up from Sleep
Start-up Time
—
5.5
12
24
μsVDD = 2.0V, -40°C to +85°C
—3.5
7
14
μsVDD = 3.0V, -40°C to +85°C
—3
6
11
μsVDD = 5.0V, -40°C to +85°C
*
These parameters are characterized but not tested.
Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1:
Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock)
for all devices.
2:
To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the
device as possible. 0.1
μF and 0.01 μF values in parallel are recommended.
3:
By design.
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