參數(shù)資料
型號(hào)： PIC12F683-I/SN
廠商： Microchip Technology
文件頁數(shù)： 126/176頁
文件大?。?/td> 0K
描述： IC MCU FLASH 2KX14 8SOIC
產(chǎn)品培訓(xùn)模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
Digi-Key 應(yīng)用說明： AN0005 PWM Example with Microchip's CCP Module
AN0005 Example Code
標(biāo)準(zhǔn)包裝： 100
系列： PIC® 12F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設(shè)備： 欠壓檢測/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 5
程序存儲(chǔ)器容量： 3.5KB（2K x 14）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 256 x 8
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
包裝： 管件
產(chǎn)品目錄頁面： 645 (CN2011-ZH PDF)
配用： AC162058-ND - HEADER MPLAB ICD2 FOR PIC12F683
I3-DB12F683-ND - BOARD DAUGHTER ICEPIC3
其它名稱： PIC12F683-I/SNG
PIC12F683-I/SNG-ND
2007 Microchip Technology Inc.
DS41211D-page 51
PIC12F683
8.0
COMPARATOR MODULE
Comparators are used to interface analog circuits to a
digital circuit by comparing two analog voltages and
providing a digital indication of their relative magnitudes.
The comparators are very useful mixed signal building
blocks because they provide analog functionality
independent of the program execution. The analog
comparator module includes the following features:
Multiple comparator configurations
Comparator output is available internally/externally
Programmable output polarity
Interrupt-on-change
Wake-up from Sleep
Timer1 gate (count enable)
Output synchronization to Timer1 clock input
Programmable voltage reference
8.1
Comparator Overview
The comparator is shown in Figure 8-1 along with the
relationship between the analog input levels and the
digital output. When the analog voltage at VIN+ is less
than the analog voltage at VIN-, the output of the
comparator is a digital low level. When the analog
voltage at VIN+ is greater than the analog voltage at
VIN-, the output of the comparator is a digital high level.
FIGURE 8-1:
SINGLE COMPARATOR
FIGURE 8-2:
COMPARATOR OUTPUT BLOCK DIAGRAM
–
+
VIN+
VIN-
Output
VIN+
VIN-
Note:
The black areas of the output of the
comparator represents the uncertainty
due to input offsets and response time.
CMSYNC
DQ
EN
To COUT pin
RD CMCON0
Set CMIF bit
MUL
T
IP
LE
X
Por
tPi
ns
Q3*RD CMCON0
Reset
To Data Bus
CINV
Timer1
clock source(1)
0
1
To Timer1 Gate
Note 1:
Comparator output is latched on falling edge of Timer1 clock source.
2:
Q1 and Q3 are phases of the four-phase system clock (FOSC).
3:
Q1 is held high during Sleep mode.
DQ
EN
CL
Q1
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