參數(shù)資料
型號： PIC12F683-I/SN
廠商： Microchip Technology
文件頁數(shù)： 166/176頁
文件大?。?/td> 0K
描述： IC MCU FLASH 2KX14 8SOIC
產(chǎn)品培訓模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
Digi-Key 應用說明： AN0005 PWM Example with Microchip's CCP Module
AN0005 Example Code
標準包裝： 100
系列： PIC® 12F
核心處理器： PIC
芯體尺寸： 8-位
速度： 20MHz
外圍設備： 欠壓檢測/復位，POR，PWM，WDT
輸入/輸出數(shù)： 5
程序存儲器容量： 3.5KB（2K x 14）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量： 128 x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
包裝： 管件
產(chǎn)品目錄頁面： 645 (CN2011-ZH PDF)
配用： AC162058-ND - HEADER MPLAB ICD2 FOR PIC12F683
I3-DB12F683-ND - BOARD DAUGHTER ICEPIC3
其它名稱： PIC12F683-I/SNG
PIC12F683-I/SNG-ND
2007 Microchip Technology Inc.
DS41211D-page 7
PIC12F683
3.0
MEMORY ORGANIZATION
3.1
Program Memory Organization
The PIC12F683 has a 13-bit program counter capable
of addressing an 8k x 14 program memory space. Only
the first 2k x 14 (0000h-07FFh) for the PIC12F683 is
physically implemented. Accessing a location above
these boundaries will cause a wraparound within the
first 2K x 14 space. The Reset vector is at 0000h and
the interrupt vector is at 0004h (see Figure 3-1).
FIGURE 3-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC12F683
3.2
Data Memory Organization
The data memory (see Figure 3-2) is partitioned into two
banks, which contain the General Purpose Registers
(GPR) and the Special Function Registers (SFR). The
Special Function Registers are located in the first 32
locations of each bank. Register locations 20h-7Fh in
Bank 0 and A0h-BFh in Bank 1 are General Purpose
Registers, implemented as static RAM. Register
locations F0h-FFh in Bank 1 point to addresses 70h-7Fh
in Bank 0. All other RAM is unimplemented and returns
‘0’ when read. RP0 of the STATUS register is the bank
select bit.
RP0
0
→ Bank 0 is selected
1
→ Bank 1 is selected
PC<12:0>
13
0000h
0004h
0005h
07FFh
0800h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
Wraps to 0000h-07FFh
Note:
The IRP and RP1 bits of the STATUS
register are reserved and should always
be maintained as ‘0’s.
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