參數(shù)資料
型號(hào)： PIC12F676
廠商： Microchip Technology Inc.
英文描述： 8-Pin, 8-Bit CMOS Enhanced FLASH Microcontroller with A/D Converter and EEPROM Data Memory(-2.5~5.5V,具ADC,閃速微控制器)
中文描述： 8引腳，8位閃存微控制器的CMOS增強(qiáng)與A / D轉(zhuǎn)換器和EEPROM數(shù)據(jù)存儲(chǔ)器（-2.5?5.5V的，具藝術(shù)發(fā)展局，閃速微控制器）
文件頁數(shù)： 61/170頁
文件大小： 4191K
代理商： PIC12F676
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 59
PIC16F62X
10.0
VOLTAGE REFERENCE
MODULE
The Voltage Reference is a 16-tap resistor ladder
network that provides a selectable voltage reference.
The resistor ladder is segmented to provide two ranges
of V
REF
values and has a power-down function to
conserve power when the reference is not being used.
The VRCON register controls the operation of the
reference as shown in Figure 10-1. The block diagram
is given in Figure 10-1.
10.1
Configuring the Voltage Reference
The Voltage Reference can output 16 distinct voltage
levels for each range.
The equations used to calculate the output of the
Voltage Reference are as follows:
if V
RR
= 1: V
REF
= (V
R
<3:0>/24) x V
DD
if V
RR
= 0: V
REF
= (V
DD
x 1/4) + (V
R
<3:0>/32) x
V
DD
The setting time of the Voltage Reference must be
considered when changing the V
REF
output
(Table 17-2). Example 10-1 shows an example of how
to configure the Voltage Reference for an output
voltage of 1.25V with V
DD
= 5.0V.
REGISTER 10-1:
VRCON REGISTER (ADDRESS: 9Fh)
FIGURE 10-1:
VOLTAGE REFERENCE BLOCK DIAGRAM
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
V
REN
V
ROE
V
RR
—
V
R3
V
R2
V
R1
V
R0
bit 7
bit 0
bit 7
V
REN
:
V
REF
Enable
1
= V
REF
circuit powered on
0
= V
REF
circuit powered down, no I
DD
drain
bit 6
V
ROE
:
V
REF
Output Enable
1
= V
REF
is output on RA2 pin
0
= V
REF
is disconnected from RA2 pin
bit 5
V
RR
:
V
REF
Range selection
1
= Low Range
0
= High Range
bit 4
Unimplemented:
Read as '0'
V
R
<3:0>
: V
REF
value selection 0
≤
V
R
[3:0]
≤
15
When V
RR
= 1: V
REF
= (V
R
<3:0>/ 24) * V
DD
When V
RR
= 0: V
REF
= 1/4 * V
DD
+ (V
R
<3:0>/ 32) * V
DD
bit 3-0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
Note
1:
R is defined in Table 17-2.
Vrr
8R
Vr3
Vr0
(From VRCON<3:0>)
16-1 Analog Mux
8R
R
R
R
R
V
REN
Vref
16 Stages
V
DD
V
SS
V
SS
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