參數(shù)資料
型號： PIC12F676
廠商： Microchip Technology Inc.
英文描述： 8-Pin, 8-Bit CMOS Enhanced FLASH Microcontroller with A/D Converter and EEPROM Data Memory(-2.5~5.5V,具ADC,閃速微控制器)
中文描述： 8引腳，8位閃存微控制器的CMOS增強與A / D轉(zhuǎn)換器和EEPROM數(shù)據(jù)存儲器（-2.5?5.5V的，具藝術(shù)發(fā)展局，閃速微控制器）
文件頁數(shù)： 25/170頁
文件大?。?/td> 4191K
代理商： PIC12F676
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 23
PIC16F62X
3.2.2.5
PIR1 Register
This register contains interrupt flag bits.
REGISTER 3-5:
PIR1 REGISTER (ADDRESS: 0Ch)
Note:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
R/W-0
R/W-0
R-0
R-0
U-0
R/W-0
R/W-0
R/W-0
EEIF
CMIF
RCIF
TXIF
—
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
EEIF:
EEPROM Write Operation Interrupt Flag bit
1
= The write operation completed (must be cleared in software)
0
= The write operation has not completed or has not been started
bit 6
CMIF
: Comparator Interrupt Flag bit
1
= Comparator output has changed
0
= Comparator output has not changed
bit 5
RCIF
: USART Receive Interrupt Flag bit
1
= The USART receive buffer is full
0
= The USART receive buffer is empty
bit 4
TXIF
: USART Transmit Interrupt Flag bit
1
= The USART transmit buffer is empty
0
= The USART transmit buffer is full
bit 3
Unimplemented
: Read as ‘0’
bit 2
CCP1IF
: CCP1 Interrupt Flag bit
Capture Mode
1
= A TMR1 register capture occurred (must be cleared in software)
0
= No TMR1 register capture occurred
Compare Mode
1
= A TMR1 register compare match occurred (must be cleared in software)
0
= No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1
TMR2IF
: TMR2 to PR2 Match Interrupt Flag bit
1
= TMR2 to PR2 match occurred (must be cleared in software)
0
= No TMR2 to PR2 match occurred
bit 0
TMR1IF
: TMR1 Overflow Interrupt Flag bit
1
= TMR1 register overflowed (must be cleared in software)
0
= TMR1 register did not overflow
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
’1’ = Bit is set
’0’ = Bit is cleared
x = Bit is unknown
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