- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365366 > PIC12F676 (Microchip Technology Inc.) 8-Pin, 8-Bit CMOS Enhanced FLASH Microcontroller with A/D Converter and EEPROM Data Memory(-2.5~5.5V,具ADC,閃速微控制器) PDF資料下載
參數(shù)資料
| 型號： | PIC12F676 |
| 廠商： | Microchip Technology Inc. |
| 英文描述： | 8-Pin, 8-Bit CMOS Enhanced FLASH Microcontroller with A/D Converter and EEPROM Data Memory(-2.5~5.5V,具ADC,閃速微控制器) |
| 中文描述： | 8引腳，8位閃存微控制器的CMOS增強(qiáng)與A / D轉(zhuǎn)換器和EEPROM數(shù)據(jù)存儲器（-2.5?5.5V的，具藝術(shù)發(fā)展局，閃速微控制器） |
| 文件頁數(shù)： | 103/170頁 |
| 文件大小： | 4191K |
| 代理商： | PIC12F676 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁當(dāng)前第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁
2003 Microchip Technology Inc.
Preliminary
DS40300C-page 101
PIC16F62X
14.6
Interrupts
The PIC16F62X has 10 sources of interrupt:
External Interrupt RB0/INT
TMR0 Overflow Interrupt
PORTB Change Interrupts (pins RB7:RB4)
Comparator Interrupt
USART Interrupt TX
USART Interrupt RX
CCP Interrupt
TMR1 Overflow Interrupt
TMR2 Match Interrupt
EEPROM
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on RESET.
The “return from interrupt” instruction,
RETFIE
, exits
interrupt routine as well as sets the GIE bit, which re-
enable RB0/INT interrupts.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag is contained in the special
register PIR1. The corresponding interrupt enable bit is
contained in special registers PIE1.
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in soft-
ware before re-enabling interrupts to avoid RB0/INT
recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 14-
15). The latency is the same for one or two cycle
instructions. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid multiple interrupt requests. Individual interrupt
flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit.
FIGURE 14-14:
INTERRUPT LOGIC
Note 1:
Individual interrupt flag bits are set
regardless
of
corresponding mask bit or the GIE bit.
the
status
of
their
2:
When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The CPU will execute a
NOP
in the cycle immediately following the
instruction which clears the GIE bit. The
interrupts which were ignored are still
pending to be serviced when the GIE bit
is set again.
TMR2IF
TMR2IE
CCP1IF
CCP1IE
CMIF
CMIE
TXIF
TXIE
RCIF
RCIE
EEIF
T0IF
T0IE
INTF
INTE
RBIF
RBIE
GIE
PEIE
Wake-up (If in SLEEP mode)
Interrupt to CPU
EEIE
TMR1IF
TMR1IE
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PIC12F680 | 8-Pin, 8-Bit CMOS Enhanced FLASH Microcontroller with Serial I/O Interface(-2.0~5.5V,串行I/O接口,閃速微控制器) |
| PIC12F681 | 8-Pin, 8-Bit CMOS Enhanced FLASH Microcontroller with Serial I/O Interface(-2.0~5.5V,串行I/O接口,閃速微控制器) |
| PIC16C164 | OTP 8-Bit High-Performance CMOS Microcontroller(主從模式，工作電壓3.0~5.5V，2路PWM的微控制器) |
| PIC16C165 | OTP 8-Bit High-Performance CMOS Microcontroller(主從模式，工作電壓3.0~5.5V，2路PWM的微控制器) |
| PIC16C174 | OTP 8-Bit High-Performance CMOS Microcontroller(主從模式，工作電壓3.0~5.5V，2路PWM的微控制器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PIC12F683 | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology |
| PIC12F683 DEVELOPMENT BOARD KIT | 制造商:Custom Computer Services (CCS) 功能描述:BOARD DEV FOR PIC12F683 |
| PIC12F683 DEVELOPMENT KIT | 功能描述:KIT DEV EMBEDDED C RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PICDEM™ 類型:MCU 適用于相關(guān)產(chǎn)品:PIC10F206，PIC16F690，PIC16F819 所含物品:板，線纜，元件，CD，PICkit 編程器 產(chǎn)品目錄頁面:659 (CN2011-ZH PDF) |
| PIC12F683_07 | 制造商:MICROCHIP 制造商全稱:Microchip Technology 功能描述:8-Pin Flash-Based, 8-Bit CMOS Microcontrollers with nanoWatt Technology |
| PIC12F683-E/MD | 功能描述:8位微控制器 -MCU 3.5KB 128 RAM 6I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。