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| 型號(hào)： | PI7C8150BMAIE |
| 廠商： | Pericom |
| 文件頁(yè)數(shù)： | 78/109頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 208-FQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
| 應(yīng)用： | * |
| 接口： | * |
| 電源電壓： | * |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-FQFP（28x28） |
| 包裝： | 管件 |
| 安裝類(lèi)型： | 表面貼裝 |
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PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 70 of 109
April 2009 – Revision 1.08
Table 10-2. GPIO Serial Data Format
Bit
Description
S_CLKOUT
[1:0]
Slot 0 PRSNT#[1:0] or device 0
0
[3:2]
Slot 1 PRSNT#[1:0] or device 1
1
[5:4]
Slot 2 PRSNT#[1:0] or device 2
2
[7:6]
Slot 3 PRSNT#[1:0] or device 3
3
[8]
Device 4
4
[9]
Device 5
5
[10]
Device 6
6
[11]
Device 7
7
[12]
Device 8
8
[13]
PI7C8150B S_CLKIN
9
[14]
Reserved
NA
[15]
Reserved
NA
The first 8 bits contain the PRSNT#[1:0] signal values for four slots, and these bits control
the S_CLKOUT[3:0] outputs. If one or both of the PRSNT#[1:0] signals are 0, that
indicates that a card is present in the slot and therefore the secondary clock for that slot is
not masked. If these clocks are connected to devices and not to slots, one or both of the bits
should be tied low to enable the clock.
The next 5 bits are the clock mask for devices; each bit enables or disables the clock for
one device. These bits control the S_CLKOUT[8:4] outputs: 0 enables the clock, and 1
disables the clock.
Bit 13 is the clock enable bit for S_CLKOUT[9], which is connected to PI7C8150B’s
S_CLKIN input.
If desired, the assignment of S_CLKOUT outputs to slots, devices, and PI7C8150B’s
S_CLKIN input can be rearranged from the assignment shown here. However, it is
important that the serial data stream format match the assignment of S_CLKOUT.
The 8 least significant bits are connected to the PRSNT# pins for the slots. The next 5 bits
are tied high to disable their respective secondary clocks because those clocks are not
connected to anything. The next bit is tied LOW because that secondary clock output is
connected to the PI7C8150B S_CLKIN input. When the secondary reset signal, S_RST_L,
is detected asserted and the primary reset signal, P_RST_L, is detected deasserted,
PI7C8150B drives GPIO[2] LOW for one cycle to load the clock mask inputs into the shift
register. On the next cycle, PI7C8150B drives GPIO[2] HIGH to perform a shift operation.
This shifts the clock mask into MSK_IN; the most significant bit is shifted in first, and the
least significant bit is shifted in last.
After the shift operation is complete, PI7C8150B tri-states the GPIO signals and can
deassert S_RST_L if the secondary reset bit is clear. PI7C8150B then ignores MSK_IN.
Control of the GPIO signal now reverts to PI7C8150B GPIO control registers. The clock
disable mask can be modified subsequently through a configuration write command to the
secondary clock control register in device-specific configuration space.
10.3
LIVE INSERTION
The GPIO[3] pin can be used, along with a live insertion mode bit, to disable transaction
forwarding.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150BMAIE-33 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150BND | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2-Port 32-Bit PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150BND-33 | 制造商:PERICOM 制造商全稱(chēng):Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BNDE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 32-Bit PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150BNDI | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2-Port 32-Bit PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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