參數(shù)資料
型號： PI7C8150BMAIE
廠商： Pericom
文件頁數(shù)： 67/109頁
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 208-FQFP
標準包裝： 24
系列： *
應用： *
接口： *
電源電壓： *
封裝/外殼： 208-BFQFP
供應商設備封裝： 208-FQFP（28x28）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 60 of 109
April 2009 – Revision 1.08
The SERR_L enable bit must be set in the command register.
Table 6-7. Assertion of P_SERR_L for Data Parity Errors
P_SERR_L
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Secondary Parity
Error Response
Bits
1 (de-asserted)
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / x
1
Read
Upstream
Primary
x / x
1
Read
Upstream
Secondary
x / x
1
Posted Write
Downstream
Primary
x / x
0
2 (asserted)
Posted Write
Downstream
Secondary
1 / 1
0
3
Posted Write
Upstream
Primary
1 / 1
1
Posted Write
Upstream
Secondary
x / x
1
Delayed Write
Downstream
Primary
x / x
1
Delayed Write
Downstream
Secondary
x / x
1
Delayed Write
Upstream
Primary
x / x
1
Delayed Write
Upstream
Secondary
x / x
X = don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
3
The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
6.4
SYSTEM ERROR (SERR_L) REPORTING
PI7C8150B uses the P_SERR_L signal to report conditionally a number of system error
conditions in addition to the special case parity error conditions described in Section 6.2.3.
Whenever assertion of P_SERR_L is discussed in this document, it is assumed that the
following conditions apply:
For PI7C8150B to assert P_SERR_L for any reason, the SERR_L enable bit must be
set in the command register.
Whenever PI7C8150B asserts P_SERR_L, PI7C8150B must also set the signaled
system error bit in the status register.
In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C8150B asserts
P_SERR_L when it detects the secondary SERR_L input, S_SERR_L, asserted and the
SERR_L forward enable bit is set in the bridge control register. In addition, PI7C8150B
also sets the received system error bit in the secondary status register.
PI7C8150B also conditionally asserts P_SERR_L for any of the following reasons:
Target abort detected during posted write transaction
Master abort detected during posted write transaction
Posted write data discarded after 2
24 (default) attempts to deliver (224 target retries
received)
Parity error reported on target bus during posted write transaction (see previous
section)
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PI7C8150BND-33 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PI7C8150BNDE 功能描述:外圍驅(qū)動器與原件 - PCI 32-Bit PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150BNDI 功能描述:外圍驅(qū)動器與原件 - PCI 2-Port 32-Bit PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
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