參數(shù)資料
型號(hào)： PI7C8150BMAIE
廠商： Pericom
文件頁(yè)數(shù)： 61/109頁(yè)
文件大?。?/td> 0K
描述： IC PCI-PCI BRIDGE ASYNC 208-FQFP
標(biāo)準(zhǔn)包裝： 24
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 208-BFQFP
供應(yīng)商設(shè)備封裝： 208-FQFP（28x28）
包裝： 管件
安裝類型： 表面貼裝
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 55 of 109
April 2009 – Revision 1.08
6.2.4
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when PI7C8150B responds as a target, it
detects a data parity error on the initiator (primary) bus and the following events occur:
PI7C8150B asserts P_PERR_L two cycles after the data transfer, if the parity error
response bit is set in the command register of primary interface.
PI7C8150B sets the parity error detected bit in the status register of the primary
interface.
PI7C8150B captures and forwards the bad parity condition to the secondary bus.
PI7C8150B completes the transaction normally.
Similarly, during upstream posted write transactions, when PI7C8150B responds as a
target, it detects a data parity error on the initiator (secondary) bus, the following events
occur:
PI7C8150B asserts S_PERR_L two cycles after the data transfer, if the parity error
response bit is set in the bridge control register of the secondary interface.
PI7C8150B sets the parity error detected bit in the status register of the secondary
interface.
PI7C8150B captures and forwards the bad parity condition to the primary bus.
PI7C8150B completes the transaction normally.
During downstream write transactions, when a data parity error is reported on the target
(secondary) bus by the target’s assertion of S_PERR_L, the following events occur:
PI7C8150B sets the data parity detected bit in the status register of secondary
interface, if the parity error response bit is set in the bridge control register of the
secondary interface.
PI7C8150B asserts P_SERR_L and sets the signaled system error bit in the status
register, if all the following conditions are met:
The SERR_L enable bit is set in the command register.
The posted write parity error bit of P_SERR_L event disable register is not
set.
The parity error response bit is set in the bridge control register of the
secondary interface.
The parity error response bit is set in the command register of the primary
interface.
相關(guān)PDF資料
PDF描述
VE-B7J-IX-F4 CONVERTER MOD DC/DC 36V 75W
AT89LP51-20JU MCU 8051 4K FLASH 20MHZ
ADUC824BSZ IC MCU 8K FLASH ADC/DAC 52MQFP
31-321 BNC CONN CRIMP RG-59
AT91SAM9XE128-QU MCU ARM9 128K FLASH 208-PQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8150BMAIE-33 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150BND 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2-Port 32-Bit PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150BND-33 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
PI7C8150BNDE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 32-Bit PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150BNDI 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2-Port 32-Bit PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*