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參數(shù)資料
| 型號： | PI7C8150B |
| 英文描述： | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| 中文描述： | PCI橋|異步2端口PCI橋 |
| 文件頁數(shù)： | 71/115頁 |
| 文件大?。?/td> | 879K |
| 代理商： | PI7C8150B |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 71 of 115
July 31, 2003 – Revision 1.031
request that is asserted. If a grant for a particular request is asserted, and a higher priority
request subsequently asserts, the arbiter de-asserts the asserted grant signal and asserts the
grant corresponding to the new higher priority request on the next PCI clock cycle. When
priorities are re-evaluated, the highest priority is assigned to the next highest priority
master relative to the master that initiated the previous transaction. The master that initiated
the last transaction now has the lowest priority in its group.
If PI7C8150B detects that an initiator has failed to assert S_FRAME_L after 16 cycles of
both grant assertion and a secondary idle bus condition, the arbiter de-asserts the grant.
To prevent bus contention, if the secondary PCI bus is idle, the arbiter never asserts one
grant signal in the same PCI cycle in which it de-asserts another. It de-asserts one grant and
asserts the next grant, no earlier than one PCI clock cycle later. If the secondary PCI bus is
busy, that is, S_FRAME_L or S_IRDY_L is asserted, the arbiter can be de-asserted one
grant and asserted another grant during the same PCI clock cycle.
8.2.2
PREEMPTION
Preemption can be programmed to be either on or off, with the default to on (offset 4Ch, bit
31=0). Time-to-preempt can be programmed to 0, 1, 2, 4, 8, 16, 32, or 64 (default is 0)
clocks. If the current master occupies the bus and other masters are waiting, the current
master will be preempted by removing its grant (GNT#) after the next master waits for the
time-to-preempt.
8.2.3
SECONDARY BUS ARBITRATION USING AN EXTERNAL
ARBITER
The internal arbiter is disabled when the secondary bus central function control pin,
S_CFN_L, is tied HIGH. An external arbiter must then be used.
When S_CFN_L is tied HIGH, PI7C8150B, reconfigures two pins to be external request
and grant pins. The S_GNT_L[0] pin is reconfigured to be the external request pin because
it’s an output. The S_REQ_L[0] pin is reconfigured to be the external grant pin because
it’s an input. When an external arbiter is used, PI7C8150B uses the S_GNT_L[0] pin to
request the secondary bus. When the reconfigured S_REQ_L[0] pin is asserted LOW after
PI7C8150B has asserted S_GNT_L[0], PI7C8150B initiates a transaction on the secondary
bus one cycle later. If grant is asserted and PI7C8150B has not asserted the request,
PI7C8150B parks AD, CBE and PAR pins by driving them to valid logic levels.
The unused secondary bus grant outputs, S_GNT_L[8:1] are driven HIGH. The unused
secondary bus request inputs, S_REQ_L[8:1], should be pulled HIGH.
8.2.4
BUS PARKING
Bus parking refers to driving the AD[31:0], CBE[3:0], and PAR lines to a known value
while the bus is idle. In general, the device implementing the bus arbiter is responsible for
parking the bus or assigning another device to park the bus. A device parks the bus when
the bus is idle, its bus grant is asserted, and the device’s request is not asserted. The AD
and CBE signals should be driven first, with the PAR signal driven one cycle later.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150B-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8150BEVB | 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8150BMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMA-33 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 32-Bit PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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