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參數(shù)資料
| 型號： | PI7C8150B |
| 英文描述： | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| 中文描述： | PCI橋|異步2端口PCI橋 |
| 文件頁數(shù)： | 37/115頁 |
| 文件大小： | 879K |
| 代理商： | PI7C8150B |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 37 of 115
July 31, 2003 – Revision 1.031
!
PI7C8150B handles these terminations in different ways, depending on the type of
transaction being performed.
Target abort
3.8.3.1
DELAYED WRITE TARGET TERMINATION RESPONSE
When PI7C8150B initiates a delayed write transaction, the type of target termination
received from the target can be passed back to the initiator. Table 3-7 shows the response
to each type of target termination that occurs during a delayed write transaction.
PI7C8150B repeats a delayed write transaction until one of the following conditions is met:
!
PI7C8150B completes at least one data transfer.
!
PI7C8150B receives a master abort.
!
PI7C8150B receives a target abort.
PI7C8150B makes 2
24
(default) or 2
32
(maximum) write attempts resulting in a response of
target retry.
Table 3-7. Delayed Write Target Termination Response
Target Termination
Normal
Response
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Returning target retry to initiator. Continue write attempts to target
Returning disconnect to initiator with first data transfer only if multiple data
phases requested.
Returning target abort to initiator. Set received target abort bit in target interface
status register. Set signaled target abort bit in initiator interface status register.
Target Retry
Target Disconnect
Target Abort
After the PI7C8150B makes 2
24
(default) attempts of the same delayed write trans-action
on the target bus, PI7C8150B asserts P_SERR_L if the SERR_L enable bit (bit 8 of
command register for the secondary bus) is set and the delayed-write-non-delivery bit is
not set. The delayed-write-non-delivery bit is bit 5 of P_SERR_L event disable register
(offset 64h). PI7C8150B will report system error. See Section 6.4 for a description of
system error conditions.
3.8.3.2
POSTED WRITE TARGET TERMINATION RESPONSE
When PI7C8150B initiates a posted write transaction, the target termination cannot be passed back
to the initiator.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150B-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8150BEVB | 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8150BMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMA-33 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMAE | 功能描述:外圍驅動器與原件 - PCI 32-Bit PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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