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參數(shù)資料
| 型號(hào)： | PI7C8150B |
| 英文描述： | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| 中文描述： | PCI橋|異步2端口PCI橋 |
| 文件頁(yè)數(shù)： | 15/115頁(yè) |
| 文件大?。?/td> | 879K |
| 代理商： | PI7C8150B |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 15 of 115
July 31, 2003 – Revision 1.031
Name
S_DEVSEL_L
Pin #
175
Pin #
A11
Type
STS
Description
Secondary Device Select (Active LOW):
Asserted by
the target indicating that the device is accepting the
transaction. As a master, PI7C8150B waits for the
assertion of this signal within 5 cycles of S_FRAME_L
assertion; otherwise, terminate with master abort. Before
tri-stated, it is driven to a de-asserted state for one cycle.
Secondary STOP (Active LOW):
Asserted by the
target indicating that the target is requesting the initiator
to stop the current transaction. Before tri-stated, it is
driven to a de-asserted state for one cycle.
Secondary LOCK (Active LOW):
Asserted by the
master for multiple transactions to complete.
Secondary Parity Error (Active LOW):
Asserted
when a data parity error is detected for data received on
the secondary interface. Before being tri-stated, it is
driven to a de-asserted state for one cycle.
Secondary System Error (Active LOW):
Can be
driven LOW by any device to indicate a system error
condition.
Secondary Request (Active LOW):
This is asserted by
an external device to indicate that it wants to start a
transaction on the secondary bus. The input is externally
pulled up through a resistor to VDD.
Secondary Grant (Active LOW):
PI7C8150B asserts
this pin to access the secondary bus. PI7C8150B de-
asserts this pin for at least 2 PCI clock cycles before
asserting it again. During idle and S_GNT_L asserted,
PI7C8150B will drive S_AD, S_CBE, and S_PAR.
Secondary RESET (Active LOW):
Asserted when any
of the following conditions are met:
1.
Signal P_RESET_L is asserted.
2.
Secondary reset bit in bridge control register in
configuration space is set.
When asserted, all control signals are tri-stated and
zeroes are driven on S_AD, S_CBE, and S_PAR.
Secondary Interface 66MHz Operation:
In synchronous mode, this input is used to specify if
PI7C8150B is running at 66MHz on the secondary side.
When HIGH, the Secondary bus may run at 66MHz.
When LOW, the Secondary bus may only run at
33MHz.
If P_M66EN is pulled LOW, the S_M66EN is also
driven LOW.
In asynchronous mode, S_M66EN is an input pin and
operates independently from P_M66EN. S_M66EN
should be pulled up to a logic “1” when the secondary
frequency is 66MHz, or pulled down to a logic “0” when
the secondary frequency is 33MHz.
Secondary Bus Central Function Control Pin:
When
tied LOW, it enables the internal arbiter. When tied
HIGH, an external arbiter must be used. S_REQ_L[0] is
reconfigured to be the secondary bus grant input, and
S_GNT_L[0] is reconfigured to be the secondary bus
request output. S_CFN_L has a weak internal pull-
down resistor.
S_STOP_L
173
B11
STS
S_LOCK_L
172
C11
STS
S_PERR_L
171
A12
STS
S_SERR_L
169
D11
I
S_REQ_L[8:0]
9, 8, 7, 6, 5, 4, 3,
2, 207
E4, E3, D2, C1,
C2, D3, A2,B3,
B4
I
S_GNT_L[8:0]
19, 18, 17, 16, 15,
14, 13, 11, 10
G1, F1, F2, G3,
F4, E1, E2,F3,
D1
TS
S_RESET_L
22
H1
O
S_M66EN
153
D15
I/OD
S_CFN_L
23
H2
I
2.2.3
CLOCK SIGNALS
Name
P_CLK
Pin #
45
Pin #
M4
Type
I
Description
Primary Clock Input:
Provides timing for all
transactions on the primary interface.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150B-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8150BEVB | 功能描述:界面開發(fā)工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8150BMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMA-33 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE |
| PI7C8150BMAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 32-Bit PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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