參數(shù)資料
型號(hào)： PI7C8150A-33
英文描述： PCI Bridge | 2-Port PCI-to-PCI Bridge
中文描述： PCI橋| 2端口PCI至PCI橋
文件頁(yè)數(shù)： 9/115頁(yè)
文件大小： 879K
代理商： PI7C8150A-33
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 9 of 115
July 31, 2003 – Revision 1.031
LIST OF TABLES
Table 2-1. Pin List – 208-pin FQFP............................................................................................................ 18
Table 2-2. Pin List – 256-pin PBGA............................................................................................................ 20
Table 3-1. PCI Transactions ........................................................................................................................ 22
Table 3-2. Write Transaction Forwarding .................................................................................................. 23
Table 3-3. Write Transaction Disconnect Address Boundaries................................................................... 26
Table 3-4. Read Prefetch Address Boundaries............................................................................................ 28
Table 3-5. Read Transaction Prefetching.................................................................................................... 28
Table 3-6. Device Number to IDSEL S_AD Pin Mapping........................................................................... 32
Table 3-7. Delayed Write Target Termination Response............................................................................ 37
Table 3-8. Response to Posted Write Target Termination........................................................................... 39
Table 3-9. Response to Delayed Read Target Termination......................................................................... 41
Table 5-1. Summary of Transaction Ordering ............................................................................................ 52
Table 6-1. Setting the Primary Interface Detected Parity Error Bit ........................................................... 60
Table 6-2. Setting Secondary Interface Detected Parity Error Bit.............................................................. 61
Table 6-3. Setting Primary Interface Master Data Parity Error Detected Bit............................................ 63
Table 6-4. Setting Secondary Interface Master Data Parity Error Detected Bit......................................... 63
Table 6-5. Assertion of P_PERR_L............................................................................................................. 64
Table 6-6. Assertion of S_PERR_L.............................................................................................................. 64
Table 6-7. Assertion of P_SERR_L for Data Parity Errors......................................................................... 65
Table 10-1. GPIO Operation....................................................................................................................... 74
Table 10-2. GPIO Serial Data Format........................................................................................................ 75
Table 11-1. Power Management Transitions .............................................................................................. 76
Table 16-1. TAP Pins ................................................................................................................................ 104
Table 16-2. JTAG Boundary Register Order............................................................................................. 106
LIST OF FIGURES
Figure 8-1 Secondary Arbiter Example.................................................................................................... 70
Figure 16-1 Test Access Port Block Diagram........................................................................................ 103
Figure 17-1 PCI Signal Timing Measurement Conditions..................................................................... 110
Figure 18-1 208-pin FQFP Package Outline......................................................................................... 112
Figure 18-2 256-pin PBGA Package Outline......................................................................................... 113
相關(guān)PDF資料
PDF描述
PI7C8150B PCI Bridge | Asynchronous 2-Port PCI Bridge
PI7C8152A ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON
PI7C81552 ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON
PI7C81552A ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON
PI7C8152 ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8150AMA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 208-Pin FQFP
PI7C8150AMA-33 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 208-Pin FQFP
PI7C8150AMAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150AMAE-33 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150AND 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-to-PCI BRIDGE
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