參數(shù)資料
型號(hào)： PI7C8150A-33
英文描述： PCI Bridge | 2-Port PCI-to-PCI Bridge
中文描述： PCI橋| 2端口PCI至PCI橋
文件頁(yè)數(shù)： 63/115頁(yè)
文件大?。?/td> 879K
代理商： PI7C8150A-33
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 63 of 115
July 31, 2003 – Revision 1.031
Table 6-3. Setting Primary Interface Master Data Parity Error Detected Bit
Primary
Parity Bit
Data
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Secondary Parity
Error Response
Bits
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
x / x
x / x
1 / x
x / x
0
0
1
0
0
0
1
0
0
0
1
0
X
= don’t care
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Table 6-4 shows setting the data parity detected bit in the status register of secondary
interface. This bit is set under the following conditions:
!
The PI7C8150B must be a master on the secondary bus.
!
The parity error response bit must be set in the bridge control register of secondary
interface.
!
The S_PERR_L signal is detected asserted or a parity error is detected on the
secondary bus.
Table 6-4. Setting Secondary Interface Master Data Parity Error Detected Bit
Secondary
Detected
Detected Bit
Parity
Transaction Type
Direction
Bus Where Error
Was Detected
Primary /
Secondary Parity
Error Response
Bits
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
0
1
0
0
0
1
0
0
0
1
0
0
X= don’t care
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Table 6-5 shows assertion of P_PERR_L. This signal is set under the following conditions:
!
PI7C8150B is either the target of a write transaction or the initiator of a read
transaction on the primary bus.
!
The parity-error-response bit must be set in the command register of primary interface.
相關(guān)PDF資料
PDF描述
PI7C8150B PCI Bridge | Asynchronous 2-Port PCI Bridge
PI7C8152A ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON
PI7C81552 ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON
PI7C81552A ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON
PI7C8152 ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8150AMA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 208-Pin FQFP
PI7C8150AMA-33 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 208-Pin FQFP
PI7C8150AMAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150AMAE-33 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8150AND 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-to-PCI BRIDGE
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