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參數(shù)資料
| 型號(hào)： | PI7C8150A-33 |
| 英文描述： | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| 中文描述： | PCI橋| 2端口PCI至PCI橋 |
| 文件頁(yè)數(shù)： | 50/115頁(yè) |
| 文件大?。?/td> | 879K |
| 代理商： | PI7C8150A-33 |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 50 of 115
July 31, 2003 – Revision 1.031
!
PI7C8150B does not collapse sequential write transactions to the same address into a
single write transaction—the PCI Local Bus Specification does not permit this
combining of transactions.
5.2
GENERAL ORDERING GUIDELINES
Independent transactions on primary and secondary buses have a relationship only when
those transactions cross PI7C8150B.
The following general ordering guidelines govern transactions crossing PI7C8150B:
!
The ordering relationship of a transaction with respect to other transactions is
determined when the transaction completes, that is, when a transaction ends with a
termination other than target retry.
!
Requests terminated with target retry can be accepted and completed in any order with
respect to other transactions that have been terminated with target retry. If the order of
completion of delayed requests is important, the initiator should not start a second
delayed transaction until the first one has been completed. If more than one delayed
transaction is initiated, the initiator should repeat all delayed transaction requests,
using some fairness algorithm. Repeating a delayed transaction cannot be contingent
on completion of another delayed transaction. Otherwise, a deadlock can occur.
!
Write transactions flowing in one direction have no ordering requirements with respect
to write transactions flowing in the other direction. PI7C8150B can accept posted write
transactions on both interfaces at the same time, as well as initiate posted write
transactions on both interfaces at the same time.
!
The acceptance of a posted memory write transaction as a target can never be
contingent on the completion of a non-locked, non-posted transaction as a master. This
is true for PI7C8150B and must also be true for other bus agents. Otherwise, a
deadlock can occur.
!
PI7C8150B accepts posted write transactions, regardless of the state of completion of
any delayed transactions being forwarded across PI7C8150B.
5.3
ORDERING RULES
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8150B | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8152A | ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON |
| PI7C81552 | ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C81552A | ENHANCED 2-PORT PCI TO PCI BRIDGE INTEL 21152 COMPARISON |
| PI7C8152 | ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150AMA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 208-Pin FQFP |
| PI7C8150AMA-33 | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 208-Pin FQFP |
| PI7C8150AMAE | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150AMAE-33 | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 2 Port PCI Bridge RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8150AND | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-to-PCI BRIDGE |
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