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參數(shù)資料
| 型號： | PI6CU877NFE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK DRIVER DDR2 52VFBGA |
| 產(chǎn)品變化通告： | Product Discontinuation 03/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 364 |
| 類型： | 時鐘緩沖器/驅(qū)動器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 存儲器，DDR2，SDRAM DIMM |
| 輸入： | SSTL-18 |
| 輸出： | SSTL-18 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 270MHz |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-VFBGA |
| 供應(yīng)商設(shè)備封裝： | 52-VFBGA（4.5x7） |
| 包裝： | 托盤 |
5
PS8689G
01/17/06
PI6CU877, PI6CUA877
PLL Clock Driver for
1.8V DDR2 Memory
Timing Requirements (Over recomended operating free-air temperature)
Symbol
Description
AVDD, VDDQ = 1.8V ±0.1V1
Units
Min
Max
tDC
Input clock duty cycle
40
60
%
tL
Stabilization time(1)
15
s
1.
Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power
up . During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback
signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and
CK maybe left floating after they have been driven low for one complete clock cycle.
FCK Clock Frequency Specifications (AVDD, VDDQ = 1.8 ±0.1V)
PI6CUx877
Part Number
Operating Clock Frequency(1,2)
Application Clock Frequency(1,3)
Units
Min
Max
Min
Max
PI6CU877
125
300
160
270
MHz
PI6CUA877
125
410
160
360
MHz
Notes:
1.
The PLL is able to handle spread spectrum induced skew.
2.
Operating clock frequency indicates a range over which the PLL is able to lock, but in which it is not required to meet the other timing parameters.
(Used for low-speed debug or production testing of DIMM modules).
3.
Application clock frequency indicates a range over which the PLL must meet all timing parameters.
08-0298
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6CU877NFEX | 功能描述:鎖相環(huán) - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6CU877NFX | 制造商:Pericom Semiconductor Corporation 功能描述:Zero Delay PLL Clock Driver Single 125MHz to 300MHz 52-Pin VFBGA T/R |
| PI6CUA877NFE | 功能描述:鎖相環(huán) - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6CUA877NFEX | 功能描述:鎖相環(huán) - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6CUA878NFE | 功能描述:鎖相環(huán) - PLL PLL Clock Driver for 1.8V DDR2 RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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