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參數(shù)資料
| 型號(hào)： | PI6CV857LAE |
| 廠商： | Pericom |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLK DVR DDR-SDRAM 48TSSOP |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Dec/2010 |
| 標(biāo)準(zhǔn)包裝： | 39 |
| 類型： | 時(shí)鐘緩沖器/驅(qū)動(dòng)器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 存儲(chǔ)器，DDR，SDRAM DIMM |
| 輸入： | SSTL-2 |
| 輸出： | SSTL-2 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:10 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 170MHz |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 48-TSSOP |
| 包裝： | 管件 |
1
PS8543D
08/17/09
Product Description
PI6CV857LPLLclockdeviceisdevelopedforregisteredDDRDIMM
applicationsThisPLLClockBufferisdesignedfor2.5VDDQand2.5V
AVDD operation and differential data input and output levels.
The device is a zero delay buffer that distributes a differential clock
inputpair(CLK,CLK)totendifferentialpairsofclockoutputs(Y[0:9],
Y[0:9]) and one differential pair feedback clock outputs
(FBOUT,FBOUT) . The clock outputs are controlled by the input
clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V
LVCMOS input (PWRDWN) and the Analog Power input (AVDD).
When input PWRDWN is low while power is applied, the input
receivers are disabled, the PLL is turned off and the differential clock
outputs are 3-stated. When the AVDD is strapped low, the PLL is
turned off and bypassed for test purposes.
When the input frequency falls below a suggested detection fre-
quency that is below the operating frequency of the PLL, the device
willenteralowpowermode.Aninputfrequencydetectioncircuitwill
detect the low frequency condition and perform the same low power
features as when the PWRDWN input is low.
The PLL in the PI6CV857L clock driver uses the input clocks (CLK,
CLK) and the feedback clocks (FBIN,FBIN) to provide high-perfor-
mance,low-skew,low-jitteroutputdifferentialclocks(Y[0:9],Y[0:9]).
The PI6CV857L is also able to track Spread Spectrum Clocking for
reduced EMI.
VDDQ
1
2
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5
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9
10
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48
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40
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38
37
35
36
34
33
32
31
30
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27
26
25
FBOUT
GND
FBIN
PWRDWN
GND
Y9
Y8
FBOUT
Y7
Y6
Y5
Y9
GND
Y0
Y1
VDDQ
GND
CLK
Y2
GND
Y3
Y4
AGND
AVDD
Product Features
PLL clock distribution optimized for Double Data Rate
SDRAM applications.
Distributes one differential clock input pair to ten differential
clock output pairs.
Inputs(CLK,CLK)and(FBIN,FBIN): SSTL_2
Input PWRDWN: LVCMOS
Outputs (Yx,Yx),(FBOUT,FBOUT): SSTL_2
External feedback pins (FBIN,FBIN) are used to
synchronize the outputs to the clock input.
Operates at AVDD = 2.5V for core circuit and internal PLL,
and VDDQ = 2.5V for differential output drivers
Packages (Pb-free & Green Available):
- Plastic 48-pin TSSOP
Block Diagram/Pin Configuration
PI6CV857L
PLL Clock Driver for
2.5V DDR-SDRAM Memory
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
Y0
Y1
PWRDWN
AVDD
FBIN
CLK
PLL
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
FBOUT
Powerdown
and Test
Logic
48-Pin
A
09-0025
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI6CV857LAEX | 功能描述:鎖相環(huán) - PLL 170 MHZ 1:10 SSTV Clock Driver RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6CV857LK | 制造商:Pericom Semiconductor Corporation 功能描述:170 MHZ 1:10 SSTV CLOCK DRIVER - Rail/Tube |
| PI6CV857LKE | 功能描述:鎖相環(huán) - PLL 170 MHZ 1:10 SSTV Clock Driver RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6CV857LKEX | 功能描述:鎖相環(huán) - PLL 170 MHZ 1:10 SSTV Clock Driver RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| PI6CV857LKX | 制造商:Pericom Semiconductor Corporation 功能描述:170 MHZ 1:10 SSTV CLOCK DRIVER - Tape and Reel |
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