4
PS8689G
01/17/06
PI6CU877, PI6CUA877
PLL Clock Driver for
1.8V DDR2 Memory
DC Specifications Recommended Operating Conditions
Symbol
Parameter
Min.
Nom.
Max.
Units
VDDQ
Output Supply Voltage
1.7
1.8
1.9
V
AVDD
Supply voltage(1)
VDDQ
VIL
Low-level input voltage(2)
OE, OS, CK, CK
0.35 x
VDDQ
VIH
High-level input voltage(2)
OE, OS, CK, CK
0.65 x
VDDQ
IOH
High-level output current, see Fig 2
-9
mA
IOL
Low-level output current, see Fig. 2
9
VIX
Input differential-pair crossing voltage
(VDDQ/2)
-0.15
(VDDQ/2)
-0.15
VIN
Input voltage level
-0.3
VDDQ +0.3
V
VID
Input differential voltage, See Fig 9
(2)
DC
0.3
VDDQ +0.4
AC
0.6
VDDQ +0.4
TA
TT
Operating free air temperature
0
70
C
Notes:
1. The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended
operating conditions and no timing parameters are guaranteed.
2. VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 9 for definition. The CK and CK,
VIH and VIL limits are used to define the DC low and high levels for the logic detect state.
IL
Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol
Parameter
Min.
Max.
Units
VDDQ, AVDD
, A
I/O supply voltage range and analog /core supply voltage range
-0.5
2.5
V
VI
Input voltage range
-0.5
VDDQ
+0.5
VO
Output voltage range
-0.5
VDDQ
+0.5
IIK
Input clamp current
-50
50
mA
IOK
Output clamp current
-50
50
IO
Continuous output current, VO = 0 to VDDQ
-50
50
IO(PWR)
Continuous current through each VDDQ or GND
-100
100
TSTG
Storage temperature
-65
150
C
Note:
1.
Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
08-0298