- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗2015 > PI6C410MAE (Pericom)IC CLK GEN INTEL PCI-EX 56-TSSOP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | PI6C410MAE |
| 寤犲晢锛� | Pericom |
| 鏂囦欢闋佹暩(sh霉)锛� | 11/21闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC CLK GEN INTEL PCI-EX 56-TSSOP |
| 鐢�(ch菐n)鍝佽畩鍖栭€氬憡锛� | Product Discontinuation Notice 11/Feb/2008 |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 35 |
| 绯诲垪锛� | PCI Express® (PCIe) |
| 椤炲瀷锛� | 鏅傞悩/闋荤巼鐧�(f膩)鐢熷櫒锛屽璺京(f霉)鐢ㄥ櫒 |
| PLL锛� | 鏄� |
| 涓昏鐩殑锛� | Intel CPU锛孭CI Express锛圥CIe锛� |
| 杓稿叆锛� | 鏅堕珨 |
| 杓稿嚭锛� | 鏅傞悩 |
| 闆昏矾鏁�(sh霉)锛� | 1 |
| 姣旂巼 - 杓稿叆:杓稿嚭锛� | 1:19 |
| 宸垎 - 杓稿叆:杓稿嚭锛� | 鐒�/鏄� |
| 闋荤巼 - 鏈€澶э細 | 400MHz |
| 闆绘簮闆诲锛� | 3.135 V ~ 3.465 V |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 56-TFSOP锛�0.240"锛�6.10mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 56-TSSOP |
| 鍖呰锛� | 绠′欢 |
绗�1闋�绗�2闋�绗�3闋�绗�4闋�绗�5闋�绗�6闋�绗�7闋�绗�8闋�绗�9闋�绗�10闋�鐣�(d膩ng)鍓嶇11闋�绗�12闋�绗�13闋�绗�14闋�绗�15闋�绗�16闋�绗�17闋�绗�18闋�绗�19闋�绗�20闋�绗�21闋�
19
PS8736F
11/12/08
PI6C410M/410MA
Clock Generator for Intel
PCI Express Mobile Chipset
AC Electrical Characteristics (VDD = 3.3卤5%, VDD_A = 3.3卤5%)
Symbol
Outputs
Parameters
Min.
Max.
Units
Notes
Trise / Tfall
CPU, SRC, DOT
Rise and fall Time
(measured between 0.175V to 0.525V)
175
700
ps
1,2
Trise / Tfall
PCI/PCIF, REF
Rise and fall Time
(measured between 0.8V to 2.0V)
0.3
1.2
ns
4
Trise / Tfall
USB
Rise and fall Time
(measured between 0.8V to 2.0V)
0.6
1.2
5
螖Trise / 螖Tfall
CPU, SRC, DOT
Rise and fall Time Variation
125
ps
1, 2
Tskew
CPU0, CPU1
CPU 鈥� CPU Skew
100
ps
1, 3
Tskew
CPU2
CPU 鈥� CPU Skew
250
Tskew
SRC
SRC 鈥� SRC Skew
250
Tskew
PCI/PCIF, REF
PCI 鈥� PCI Skew / REF - REF Skew (measured at
1.5V)
500
4
Tjitter
CPU0, CPU1
Cycle 鈥� Cycle Jitter
85
1, 3
Tjitter
CPU2
Cycle 鈥� Cycle Jitter
125
Tjitter
SRC
Cycle 鈥� Cycle Jitter
125
Tjitter
DOT
Cycle 鈥� Cycle Jitter
250
Tjitter
PCI/PCIF
Cycle 鈥� Cycle Jitter (measured at 1.5V)
500
4
Tjitter
USB
Cycle 鈥� Cycle Jitter (measured at 1.5V)
350
5
Tjitter
REF
Cycle 鈥� Cycle Jitter (measured at 1.5V)
1000
4
VHIGH
CPU, SRC, DOT
Voltage HIGH including overshoot
660
1150
mV
1, 2
VLOW
CPU, SRC, DOT
Voltage LOW including undershoot
-300
Vcross
CPU, SRC, DOT
Absolute crossing poing voltages
250
550
螖Vcross
CPU, SRC, DOT
Total variation of Vcross over all edges
140
TDC
CPU*, SRC, DOT
Duty-Cycle
45
55
%
1, 3
TDC
CPU0
Duty Cycle
48
52
%
1,3,6
TDC
REF, USB, PCI/PCIF Duty-Cycle (measured at 1.5V)
45
55
%
4, 5
Tstable
All clock stabilization from power-up
<1.8
ms
Fig 2
Tdrive
Differential output enable after PwrDwn de-asser-
tion
300
渭s
Pwrdwn
Trise / Tfall
Power down rise and fall time
5.0
ns
Pwrdwn
Notes:
* = Except CPU0
1. Test conguration is Rs = 33.2惟, Rp = 49.9惟, and CL = 2pF.
2. Single-Ended measurement.
3. Differential measurement.
4. PCI, PCIF, and REF CL(min) = 10pF, CL(max) = 30pF.
5. USB CL(min) = 10pF, CL(max) = 20pF.
6. CPU measured at 333 MHz
08-0298
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| PI6C410MAEX | 鍔熻兘鎻忚堪:閹栫浉鐠�(hu谩n) - PLL 3.3V Clock Generator for Intel RoHS:鍚� 鍒堕€犲晢:Silicon Labs 椤炲瀷:PLL Clock Multiplier 闆昏矾鏁�(sh霉)閲�:1 鏈€澶ц几鍏ラ牷鐜�:710 MHz 鏈€灏忚几鍏ラ牷鐜�:0.002 MHz 杓稿嚭闋荤巼鑼冨湇:0.002 MHz to 808 MHz 闆绘簮闆诲-鏈€澶�:3.63 V 闆绘簮闆诲-鏈€灏�:1.71 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:QFN-36 灏佽:Tray |
| PI6C410V | 鍒堕€犲晢:PERICOM 鍒堕€犲晢鍏ㄧū:Pericom Semiconductor Corporation 鍔熻兘鎻忚堪:Clock Generator for Intel PCI-Express Desktop Chipset |
| PI6C410VE | 鍔熻兘鎻忚堪:閹栫浉鐠�(hu谩n) - PLL 3.3V Clock Generator for Intel RoHS:鍚� 鍒堕€犲晢:Silicon Labs 椤炲瀷:PLL Clock Multiplier 闆昏矾鏁�(sh霉)閲�:1 鏈€澶ц几鍏ラ牷鐜�:710 MHz 鏈€灏忚几鍏ラ牷鐜�:0.002 MHz 杓稿嚭闋荤巼鑼冨湇:0.002 MHz to 808 MHz 闆绘簮闆诲-鏈€澶�:3.63 V 闆绘簮闆诲-鏈€灏�:1.71 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:QFN-36 灏佽:Tray |
| PI6C410VEX | 鍔熻兘鎻忚堪:閹栫浉鐠�(hu谩n) - PLL 3.3V Clock Generator for Intel RoHS:鍚� 鍒堕€犲晢:Silicon Labs 椤炲瀷:PLL Clock Multiplier 闆昏矾鏁�(sh霉)閲�:1 鏈€澶ц几鍏ラ牷鐜�:710 MHz 鏈€灏忚几鍏ラ牷鐜�:0.002 MHz 杓稿嚭闋荤巼鑼冨湇:0.002 MHz to 808 MHz 闆绘簮闆诲-鏈€澶�:3.63 V 闆绘簮闆诲-鏈€灏�:1.71 V 鏈€澶у伐浣滄韩搴�:+ 85 C 鏈€灏忓伐浣滄韩搴�:- 40 C 灏佽 / 绠遍珨:QFN-36 灏佽:Tray |
| PI6C41202 | 鍒堕€犲晢:PERICOM 鍒堕€犲晢鍏ㄧū:Pericom Semiconductor Corporation 鍔熻兘鎻忚堪:LVCMOS to LVPECL Driver |
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