參數(shù)資料
型號(hào)： PHT1N52S
廠商： NXP SEMICONDUCTORS
元件分類： JFETs
英文描述： PowerMOS transistor
中文描述： 0.6 A, 520 V, 10 ohm, N-CHANNEL, Si, POWER, MOSFET
文件頁數(shù)： 2/5頁
文件大?。?/td> 27K
代理商： PHT1N52S
Philips Semiconductors
Objective specification
PowerMOS transistor
PHT1N52S
THERMAL RESISTANCES
SYMBOL
PARAMETER
R
th j-sp
Thermal resistance junction to
solder point
R
th j-a
Thermal resistance junction to
ambient
CONDITIONS
MIN.
-
TYP.
-
MAX.
15
UNIT
K/W
pcb mounted; minimum footprint
pcb mounted; pad area as in fig:2
-
-
156
70
-
-
K/W
K/W
STATIC CHARACTERISTICS
T
mb
= 25 C unless otherwise specified
SYMBOL
PARAMETER
V
(BR)DSS
Drain-source breakdown volt-
age
V
GS(TO)
Gate threshold voltage
I
DSS
Drain-source leakage current
CONDITIONS
V
GS
= 0 V; I
D
= 0.25 mA
MIN.
520
TYP.
-
MAX.
-
UNIT
V
V
DS
= V
; I
= 0.25 mA
V
DS
= 500 V; V
GS
= 0 V; T
j
= 25 C
V
DS
= 400 V; V
GS
= 0 V; T
j
= 125 C
V
GS
=
±
35 V; V
= 0 V
V
GS
= 10 V; I
D
= 1 A
2.0
-
-
-
-
3.0
1
0.1
4
7.9
4.0
100
1.0
100
10
V
μ
A
mA
nA
I
GSS
R
DS(ON)
Gate-source leakage current
Drain-source on-state resis-
tance
Source-drain diode forward
voltage
V
SD
I
F
= 2 A ;V
GS
= 0 V
-
0.85
1.2
V
DYNAMIC CHARACTERISTICS
T
mb
= 25 C unless otherwise specified
SYMBOL
PARAMETER
g
fs
Forward transconductance
C
iss
Input capacitance
C
oss
Output capacitance
C
rss
Feedback capacitance
Q
g(tot)
Total gate charge
Q
gs
Gate to source charge
Q
gd
Gate to drain (Miller) charge
t
d on
Turn-on delay time
t
r
Turn-on rise time
t
d off
Turn-off delay time
t
f
Turn-off fall time
t
rr
Source-drain diode Reverse
recovery time
Q
rr
Source-drain diode Reverse
recovery charge
CONDITIONS
V
DS
= 15 V; I
D
= 1 A
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz
MIN.
0.5
-
-
-
-
-
-
-
-
-
-
-
TYP.
0.8
75
10
5
5
.5
3
5
15
15
7
150
MAX.
-
100
15
10
-
-
-
10
20
20
15
-
UNIT
S
pF
pF
pF
nC
nC
nC
ns
ns
ns
ns
ns
V
GS
= 10 V; I
D
= 2 A; V
DS
= 400 V
V
DD
= 30 V; I
D
= 2 A;
V
GS
= 10 V; R
GS
= 50
;
R
GEN
= 50
I
F
= 2 A; -dI
F
/dt = 100 A/
μ
s;
V
GS
= 0 V; V
R
= 100 V
-
1.5
-
μ
C
February 1998
2
Rev 1.000
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