參數(shù)資料
型號(hào)： PHT1N52S
廠商： NXP SEMICONDUCTORS
元件分類： JFETs
英文描述： PowerMOS transistor
中文描述： 0.6 A, 520 V, 10 ohm, N-CHANNEL, Si, POWER, MOSFET
文件頁(yè)數(shù)： 1/5頁(yè)
文件大小： 27K
代理商： PHT1N52S
Philips Semiconductors
Objective specification
PowerMOS transistor
PHT1N52S
GENERAL DESCRIPTION
QUICK REFERENCE DATA
N-channel
field-effect power transistor in a
plastic envelope suitable for surface
mounting featuring high avalanche
energy capability, stable blocking
voltage, fast switching and high
thermal
cycling
Intended for use in Compact Fluor-
escent Lights (CFL) and general
purpose switching applications.
enhancement
mode
SYMBOL
PARAMETER
MAX.
UNIT
V
DS
I
D
P
tot
R
DS(ON)
Drain-source voltage
Drain current (DC)
Total power dissipation
Drain-source on-state resistance
520
0.6
1.8
10
V
A
W
performance.
PINNING - SOT223
PIN CONFIGURATION
SYMBOL
PIN
DESCRIPTION
1
gate
2
drain
3
source
4
drain (tab)
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
V
DS
Drain-source voltage
V
DGR
Drain-gate voltage
±
V
GS
Gate-source voltage
I
D
Drain current (DC)
CONDITIONS
MIN.
-
-
-
-
-
-
MAX.
520
520
30
0.6
0.5
2.4
UNIT
V
V
V
A
A
A
R
GS
= 20 k
T
sp
= 25 C
T
sp
= 100 C
T
sp
= 25 C
I
DM
Drain current (pulse peak
value)
Source-drain diode current
(DC)
Source-drain diode current
(pulse peak value)
Total power dissipation
Storage temperature
Junction temperature
I
DR
T
sp
= 25 C
-
0.6
A
I
DRM
T
sp
= 25 C
-
2.4
A
P
tot
T
stg
T
j
T
sp
= 25 C
-
1.8
150
150
W
C
C
-55
-
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
W
DSS
Drain-source non-repetitive
unclamped inductive turn-off
energy
CONDITIONS
I
D
= 1 A ; V
DD
≤
50 V ; V
GS
= 10 V ;
R
GS
= 50
MIN.
MAX.
UNIT
T
= 25C prior to surge
T
= 100C prior to surge
-
-
-
25
10
3.6
mJ
mJ
mJ
W
DSR
1
Drain-source repetitive
unclamped inductive turn-off
energy
I
D
= 1 A ; V
DD
≤
50 V ; V
GS
= 10 V ;
R
GS
= 50
j
≤
150 C
1. Pulse width and frequency limited by T
j(max)
4
1
2
3
d
g
s
February 1998
1
Rev 1.000
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