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參數(shù)資料
| 型號： | PHB2N50E |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | JFETs |
| 英文描述： | PowerMOS transistors Avalanche energy rated |
| 中文描述： | 2 A, 500 V, 5 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | SOT-404, 3 PIN |
| 文件頁數(shù)： | 2/10頁 |
| 文件大小： | 75K |
| 代理商： | PHB2N50E |
Philips Semiconductors
Product specification
PowerMOS transistors
Avalanche energy rated
PHP2N50E, PHB2N50E, PHD2N50E
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
E
AS
Non-repetitive avalanche
energy
CONDITIONS
Unclamped inductive load, I
= 1.26 A;
t
p
= 0.2 ms; T
j
prior to avalanche = 25C;
V
≤
50 V; R
GS
= 50
; V
GS
= 10 V; refer
to fig:17
MIN.
-
MAX.
82
UNIT
mJ
E
AR
Repetitive avalanche energy
2
I
= 2 A; t
= 2.5
μ
s; T
prior to
-
3.3
mJ
avalanche = 25C; R
GS
= 50
; V
GS
= 10 V;
refer to fig:18
I
AS
, I
AR
Repetitive and non-repetitive
avalanche current
-
2
A
THERMAL RESISTANCES
SYMBOL PARAMETER
R
th j-mb
Thermal resistance junction
to mounting base
R
th j-a
Thermal resistance junction
to ambient
CONDITIONS
MIN.
-
TYP. MAX. UNIT
-
2.5
K/W
SOT78 package, in free air
SOT404 and SOT428 packages, pcb
mounted, minimum footprint
-
-
60
50
-
-
K/W
K/W
2
pulse width and repetition rate limited by T
j
max.
December 1998
2
Rev 1.200
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