- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369995 > PF48F3P0ZBQ0 (Intel Corp.) Intel StrataFlash Embedded Memory PDF資料下載
參數(shù)資料
| 型號： | PF48F3P0ZBQ0 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Embedded Memory |
| 中文描述： | 英特爾StrataFlash嵌入式存儲器 |
| 文件頁數(shù)： | 52/102頁 |
| 文件大?。?/td> | 1609K |
| 代理商： | PF48F3P0ZBQ0 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁當前第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁
1-Gbit P30 Family
April 2005
52
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
Write
0x10
Alternate Word
Program Setup
Equivalent to the Word Program Setup command, 0x40.
0xE8
Buffered Program
This command loads a variable number of words up to the buffer size of 32
words onto the program buffer.
The confirm command is Issued after the data streaming for writing into the
buffer is done. This instructs the WSM to perform the Buffered Program
algorithm, writing the data from the buffer to the flash memory array.
First cycle of a 2-cycle command; initiates Buffered Enhanced Factory
Program mode (BEFP). The CUI then waits for the BEFP Confirm command,
0xD0, that initiates the BEFP algorithm. All other commands are ignored when
BEFP mode begins.
If the previous command was BEFP Setup (0x80), the CUI latches the address
and data, and prepares the device for BEFP mode.
First cycle of a 2-cycle command; prepares the CUI for a block-erase
operation. The WSM performs the erase algorithm on the block addressed by
the Erase Confirm command. If the next command
is not
the Erase Confirm
(0xD0) command, the CUI sets Status Register bits SR[4] and SR[5], and
places the device in read status register mode.
If the first command was Block Erase Setup (0x20), the CUI latches the
address and data, and the WSM erases the addressed block. During block-
erase operations, the device responds only to Read Status Register and Erase
Suspend commands. CE# or OE# must be toggled to update the Status
Register in asynchronous read. CE# or ADV# must be toggled to update the
Status Register Data for synchronous Non-array reads
This command issued to any device address initiates a suspend of the
currently-executing program or block erase operation. The Status Register
indicates successful suspend operation by setting either SR[2] (program
suspended) or SR[6] (erase suspended), along with SR[7] (ready). The Write
State Machine remains in the suspend mode regardless of control signal states
(except for RST# asserted).
This command issued to any device address resumes the suspended program
or block-erase operation.
First cycle of a 2-cycle command; prepares the CUI for block lock configuration
changes. If the next command is not Block Lock (0x01), Block Unlock (0xD0),
or Block Lock-Down (0x2F), the CUI sets Status Register bits SR[4] and SR[5],
indicating a command sequence error.
If the previous command was Block Lock Setup (0x60), the addressed block is
locked.
If the previous command was Block Lock Setup (0x60), the addressed block is
unlocked. If the addressed block is in a lock-down state, the operation has no
effect.
If the previous command was Block Lock Setup (0x60), the addressed block is
locked down.
First cycle of a 2-cycle command; prepares the device for a Protection Register
or Lock Register program operation. The second cycle latches the register
address and data, and starts the programming algorithm
First cycle of a 2-cycle command; prepares the CUI for device read
configuration. If the Set Read Configuration Register command (0x03) is not
the next command, the CUI sets Status Register bits SR[4] and SR[5],
indicating a command sequence error.
If the previous command was Read Configuration Register Setup (0x60), the
CUI latches the address and writes A[15:0] to the Read Configuration Register.
Following a Configure Read Configuration Register command, subsequent
read operations access array data.
0xD0
Buffered Program
Confirm
0x80
BEFP Setup
0xD0
BEFP Confirm
Erase
0x20
Block Erase Setup
0xD0
Block Erase Confirm
Suspend
0xB0
Program or Erase
Suspend
0xD0
Suspend Resume
Block Locking/
Unlocking
0x60
Lock Block Setup
0x01
Lock Block
0xD0
Unlock Block
0x2F
Lock-Down Block
Protection
0xC0
Program Protection
Register Setup
Configuration
0x60
Read Configuration
Register Setup
0x03
Read Configuration
Register
Table 21.
Command Codes and Definitions (Sheet 2 of 2)
Mode
Code
Device Mode
Description
相關PDF資料 |
PDF描述 |
|---|---|
| PF48F4P0ZBQ0 | Intel StrataFlash Embedded Memory |
| PF48F4P0VB00 | Photoelectric Sensor; Sensor Input Type:Optical; Sensing Range Max:43mm; Sensor Output Type:Relay; Leaded Process Compatible:No; Output Type:Relay; Peak Reflow Compatible (260 C):No; Contact Current Max:3A; Contact Rating:3A |
| PF48F0P0VT00 | Intel StrataFlash Embedded Memory |
| PF48F2P0VT00 | Intel StrataFlash Embedded Memory |
| PF48F3P0VT00 | Intel StrataFlash Embedded Memory |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PF48F3P0ZT00 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F3P0ZTQ0 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Embedded Memory |
| PF48F4000M0Y0CEA | 制造商:Micron Technology Inc 功能描述:256BA/0BA SCSP 1.8 X16C HF - Trays |
| PF48F4000P0ZB | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:Micron Parallel NOR Flash Embedded Memory (P30-65nm) |
| PF48F4000P0ZBQ0 | 制造商:NUMONYX 制造商全稱:Numonyx B.V 功能描述:Numonyx StrataFlash Embedded Memory |
發(fā)布緊急采購，3分鐘左右您將得到回復。