參數(shù)資料
型號(hào)： PF48F3P0ZBQ0
廠商： Intel Corp.
英文描述： Intel StrataFlash Embedded Memory
中文描述： 英特爾StrataFlash嵌入式存儲(chǔ)器
文件頁數(shù)： 22/102頁
文件大?。?/td> 1609K
代理商： PF48F3P0ZBQ0
1-Gbit P30 Family
April 2005
22
Intel StrataFlash
Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
4.3
SCSP Configurations
WP#
Input
WRITE PROTECT:
Active low input. WP# low enables the lock-down mechanism. Blocks in lock-
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
VPP
Power/
lnput
Erase and Program Power:
A valid voltage on this pin allows erasing or programming. Memory
contents cannot be altered when V
PP
≤
V
PPLK
. Block erase and program at invalid V
PP
voltages
should not be attempted.
Set V
= V
for in-system program and erase operations. To accommodate resistor or diode drops
from the system supply, the V
level of V
can be as low as V
min. V
must remain above V
PPL
min to perform in-system flash modification. VPP may be 0 V during read operations.
V
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
cycles.
VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
VCC
Power
Device Core Power Supply:
Core (logic) source voltage. Writes to the flash array are inhibited when
V
CC
≤
V
LKO
. Operations at invalid V
CC
voltages should not be attempted.
VCCQ
Power
Output Power Supply:
Output-driver source voltage.
VSS
Power
Ground:
Connect to system ground. Do not float any VSS connection.
RFU
—
Reserved for Future Use:
Reserved by Intel for future device functionality and enhancement. These
should be treated in the same way as a Do Not Use (DU) signal.
DU
—
Do Not Use:
Do not connect to any other signal, or power supply; must be left floating.
NC
—
No Connect:
No internal connection; can be driven or floated.
Table 4.
QUAD+ SCSP Signal Descriptions (Sheet 2 of 2)
Symbol
Type
Name and Function
Table 5.
Stacked Easy BGA Chip Select Logic
Stack Combination
Selected Flash
Die #1
Selected Flash
Die #2
1-die
F1-CE#
-
2-die
F1-CE# + A25 (V
IL
)
F1-CE# + A25 (V
IH
)
Table 6.
QUAD+ SCSP Chip Select Logic
Stack
Combination
Selected Flash
Die #1
Selected Flash
Die #2
Selected Flash
Die #3
Selected Flash
Die #4
1-die
F1-CE#
-
-
-
2-die
F1-CE# + A24 (V
IL
)
F1-CE# + A24 (V
IH
)
-
-
4-die
F1-CE# + A24 (V
IL
)
F1-CE# + A24 (V
IH
)
F2-CE# + A24 (V
IL
)
F2-CE# + A24 (V
IH
)
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