- 您現在的位置：買賣IC網 > PDF目錄378048 > PEB2445N (SIEMENS AG) LTM4600 Evaluation Kit PDF資料下載
參數資料
| 型號： | PEB2445N |
| 廠商： | SIEMENS AG |
| 英文描述： | LTM4600 Evaluation Kit |
| 中文描述： | ？多點交換和會議股-衰減？ |
| 文件頁數： | 39/70頁 |
| 文件大?。?/td> | 1236K |
| 代理商： | PEB2445N |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁當前第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁
PEB 2445
Operational Description
Semiconductor Group
39
02.96
3
Operational Description
3.1
After a hardware reset (RES) or power up the MUSAC-A is set to its initial state. The
MOD- and CFR register bits are all set to logical 1; the CSR-, CST- and CMR-register
bits are set to logical 0. The STA register
B
bit is undefined, the
Z
bit contains logical 0.
Reset State
3.2
After reset a few internal signals and clocks need to be initialized. This is done with the
initialization sequence. To give all signals and clocks a defined value only 4 SP pulses
are necessary. The SP pulses may be of any length allowed in normal application, the
time interval between the two SP pulses may be of any length down to 250 ns.
With all signals being defined, the CM needs to be reset. To do that a logical 0 is written
into MOD:RC. STA:B is set. The resulting CM reset is finished after max. 250
μ
s and is
indicated by the status register B bit being logical 0. Changing the pulse shaping factor
N during CM reset may result in a CM-reset time longer than 250
μ
s.
After resetting the CM, all bits in the CM are reset to 0, except for the D9-bit, which is set
to one, causing the output lines to be tristated.
To prepare the MUSAC-A for programming the CM and CCM, the Rl bit in the mode
register must be reset. Note that one mode register access can serve to reset both RC-
and Rl bits as well as configuring the chip (i.e. selecting operating mode etc.).
Initialization Procedure
Figure 18
Initializing the PEB 2445 for a 8192-kHz Device Clock
相關PDF資料 |
PDF描述 |
|---|---|
| PEB2447 | Memory Time Switch Extended Large MTSXL |
| PEB2447H | Memory Time Switch Extended Large MTSXL |
| PEB2466 | Four Channel Codec Filter with PCM- and m-Controller Interface SICOFI4-mC |
| PEB2466-HV1.2 | Four Channel Codec Filter with PCM- and m-Controller Interface SICOFI4-mC |
| PEB24902 | Quad ISDN Echocancellation Circuit Analogue Front End Quad IEC AFE |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PEB2445-N | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Multipoint Switching and Conferencing Unit - Attenuation MUSAC-A |
| PEB2445P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM， Other/Special/Miscellaneous |
| PEB2447 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Memory Time Switch Extended Large MTSXL |
| PEB2447H | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Memory Time Switch Extended Large MTSXL |
| PEB2447HV1.2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復。