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參數(shù)資料
| 型號： | PEB2445N |
| 廠商： | SIEMENS AG |
| 英文描述： | LTM4600 Evaluation Kit |
| 中文描述： | ？多點交換和會議股-衰減？ |
| 文件頁數(shù)： | 30/70頁 |
| 文件大小： | 1236K |
| 代理商： | PEB2445N |
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PEB 2445
Functional Description
Semiconductor Group
30
02.96
Figure 13
shows when the single bits are output. In standard configuration they are
clocked off at the rising clock edge at the beginning of the considered bit period.
Time-slot 0 starts two
t
CP8
before the falling edge of the SP pulse.
In primary access configuration the even output lines are affected by the XS2, XS1, XS0
and XFE entries in the clock shift register. The output frame is synchronized with the
rising edge of the SP signal.
Assuming a
CSR
entry X0
H
the output frame starts with the rising edge of the SP pulse.
Programming the XS2, XS1 and XS0 bits with a value deviating from binary 000 the
output frame is delayed by 8
D
– (XS2, XS1, XS0)
B
bit periods. E.g, a
CSR
entry of
(XXXX0010) delays the output frame by 7-bit periods relative to the rising SP-pulse
edge.
Programming
CSR:(XXXXXXX1)
the output frame is delayed by another half a
device
clock period. In
figure 13
the outputting instants are shown for a device clock of 4096
and 8192 kHz and a
CSR:(XXXX0001)
.
The last line in
figure 13
shows an even 8192-kbit/s output line for the
CSR
entry
(XXXX1101) and an 8192-kHz device clock. The output frame is delayed by 2 1/2-bit
periods. For further examples refer to
figure 20
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PEB2445-N | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Multipoint Switching and Conferencing Unit - Attenuation MUSAC-A |
| PEB2445P | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM， Other/Special/Miscellaneous |
| PEB2447 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Memory Time Switch Extended Large MTSXL |
| PEB2447H | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Memory Time Switch Extended Large MTSXL |
| PEB2447HV1.2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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