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參數(shù)資料
| 型號： | PE12316 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Triple Incremental Encoder |
| 中文描述： | 三增量編碼器 |
| 文件頁數(shù)： | 16/29頁 |
| 文件大?。?/td> | 1542K |
| 代理商： | PE12316 |
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PE12316
Triple
Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
Timing Requirements over Recommended Operating Conditions
Symbol
Parameter
February 6, 2003 (Preliminary Version 1.1)
Page 16/29
PE12316
MIN
TYP
MAX
Units
Tc1
CLK Cycle Time, duty cycle 50%
50
ns
Tc2
Pulse width low CLK
25
ns
Twrs
Pulse width, /RESET input low
50
ns
fmud
Maximum frequency, /UPn or /DOWNn,
Input duty cycle 50%
20
25
MHz
Twud
Pulse width, /UPn or /DOWNn input low
25
ns
Twk
Pulse width, /KLI-KLOn input low
20
ns
Twrd1
Pulse width, /RD input low (Mode = 6 & 7)
ns
Twrd2
Pulse width, /RD input low (Mode = 0 to 5)
Tc1
ns
Tdrd
Time between two read cycles (LSB and MSB)
0
ns
Twwr
Pulse width, /WE input low
25
ns
Tdwr
Time between two read cycles (LSB and MSB)
0
ns
Tsd
Set up time, DATA prior to /WE
rising
15
ns
Tsus
Set up time, /CS and /RD low before CLK falling edge
15
ns
Tsa
Set up time, /A0, /A1, /A2 prior to /WE and /CS low
10
ns
Tsud
Set up time, /UPn or /DOWNn rising edge before CLK
falling edge
20
ns
Tsab
Set up time, Ua1n or Ua2n prior to CLK falling edge.
15
ns
Tsda
Set up time, DATA prior to /WE
rising
Tsd
ns
Tsbb
Set up time, Ua2n stable before CLK falling edge
15
ns
Tsac
Set up time, Ua1 or Ua2 rising edge before CLK falling
edge.
15
ns
Tsar
Set up time, /A0, /A1, /A2 stable before /CS and /RD
low after reset
10
ns
Tsbc
Set up time, Ua1n or Ua2n falling edge
15
ns
Tsr
Set up time, /RESET high prior to CLK falling edge.
0
ns
Tsuc
Set up time, /UPn or /DOWNn rising edge prior to
/KLI-KLOn (input) falling edge.
20
ns
Thdw
Hold time DATA after /WE rising
10
ns
Twgp
Pulse width, Ua1n input high (Mode = 6)
Min 2 x Tc1
ns
Twgp
Pulse width, Ua2n input high (Mode = 7)
Min 2 x Tc1
ns
Tdgp
Pulse width, Ua1n input low (Mode = 6)
Min 2 x Tc1
ns
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