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參數(shù)資料
| 型號： | PE12316 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Triple Incremental Encoder |
| 中文描述： | 三增量編碼器 |
| 文件頁數(shù)： | 12/29頁 |
| 文件大?。?/td> | 1542K |
| 代理商： | PE12316 |
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PE12316
Triple
Incremental Encoder
February 6, 2003 Preliminary (Version 1.1)
Configuration
Special consideration should be paid to the
automatic
configuration
PE12316. The purpose of these features is to
allow for the different order of byte reads (high
then low or low then high) of different processors
Byte order Configuration
After a system reset has occurred, the first read
operation will store the value of /A0 and /A3 in a
latch within the device. From that time until the
next system reset the load output register pulse
during a read operation will only be generated if
/A0 and /A3 are this stored value. This means
that the
Cascaded configuration
After a system reset the first device and channel
to receive a read operation configures itself into
‘Master’ mode and outputs a pulse on /KLI-KLO.
In cascaded operation the /KLI-KLO pins of the
cascaded channels are connected together and
the input pulse on /KLI-KLO of the cascaded
channels configures these to ‘Slave’ mode. On
all subsequent read operations the load output
register pulse is only generated by the ‘Master’
channel (for the appropriate polarity of /A0, as
noted above) and this is fed to the ‘Slave’
devices via the /KLI-KLO connection.
Special care should be taken when cascading
devices or channels to always read in the same
channel order, as well as the byte order already
mentioned.
February 6, 2003 (Preliminary Version 1.1)
Page 12/29
PE12316
features
of
the
when doing a word read across a byte wide bus
and also to configure cascaded devices
automatically for correct word read sequence –
see below.
internal load output register pulse is correctly
generated for word operations regardless of the
byte order of the particular processor. Special
care should be taken if reading individual bytes
to ensure these operations are always done in
a consistent order.
To freeze all three channels with a single read
cycle (in cascaded or non-cascaded mode) the
/KLI-KLOn pins of all channels are connected
with a pull-up resistor to V
CC
(see System
Application). This ensures that only one
channel is operating as the ‘Master’ and all
others are ‘Slaves’.
If an external “freeze” of the positioning system
is required, an external /KLI-KLO pulse will
program all channels as slaves. This is derived
by generating an external /KLI-KLO pulse
before
the first read cycle appears after system
reset.
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