參數(shù)資料
型號(hào)： PDI1394L21BE
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 1394 full duplex AV link layer controller
中文描述： 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100
封裝： 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, SOT-407-1, LQFP-100
文件頁(yè)數(shù)： 30/42頁(yè)
文件大?。?/td> 233K
代理商： PDI1394L21BE
Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
30
without any packet data. A null packet is transmitted whenever the
packet speed exceeds the capability of the receiving PHY, or
whenever the LLC immediately releases the bus without transmitting
any data. In this case, the PHY will assert Receive on the CTL
terminals with the “data-on” indication (all 1’s) on the D terminals,
followed by Idle on the CTL terminals, without any speed code or
data being transferred. In all cases, in normal operation, the
PDI1394P23 sends at least one “data-on” indication before sending
the speed code or terminating the receive operation.
The PDI1394P23 also transfers its own self-ID packet, transmitted
during the self-ID phase of bus initialization to the LLC. This packet
is transferred to the LLC just as any other received self-ID packet.
The sequence of events for a normal packet reception is as follows:
Receive operation initiated. The PHY indicates a receive
operation by asserting Receive on the CTL lines. Normally, the
interface is idle when receive is asserted. However, the receive
operation may interrupt a status transfer operation that is in
progress so that the CTL lines may change from status to receive
without an intervening idle.
Data-on indication. The PHY may assert the data-on indication code
on the D lines for one or more cycles preceding the speed code.
Speed code. the PHY indicates the speed of the received packet
by asserting a speed code on the D lines for one cycle
immediately preceding packet data. The link decodes the speed
code on the first Receive cycle for which the D lines are not the
data-on code. If the speed code is invalid, or indicates a speed
higher than that which the link is capable of handling, the link
should ignore the subsequent data.
Receive data. Following the data-on indication (if any) and the
speed code, the PHY asserts packet data on the D lines with
receive on the CTL lines for the remainder of the receive operation.
Receive operation terminated. The PHY terminates the receive
operation by asserting the idle on the CTL lines. The PHY asserts
at least one cycle of idle following a receive operation.
SYSCLK
(a)
(b)
CTL0, CTL1
D0–D7
XX
00
00
10
00
01
dn
FF (“data-on”)
SV01760
(e)
d0
SPD
(c)
(d)
NOTE:
SPD = Speed code; see Table 19; d0–dn = Packet data.
Figure 16.
Normal Packet Reception Timing
The sequence of events for a null packet reception is as follows:
Receive operation initiated. The PHY indicates a receive
operation by asserting receive on the CTL lines. Normally, the
interface is idle when receive is asserted. However, the receive
operation may interrupt a status transfer operation that is in
progress so that the CTL lines may change from status to receive
without an intervening idle.
Data-on indication. The PHY asserts the data-on indication code
on the D lines for one or more cycles.
Receive operation terminated. The PHY terminates the receive
operation by asserting Idle on the CTL lines. The PHY shall
assert at least one cycle of Idle following a receive operation.
SYSCLK
(a)
(b)
CTL0, CTL1
D0–D7
XX
00
00
10
00
01
FF (“data-on”)
SV01761
(c)
Figure 17.
Null Packet Reception Timing
相關(guān)PDF資料
PDF描述
PDI1394L21BP 1394 full duplex AV link layer controller
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參數(shù)描述
PDI1394L21BP 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller
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PDI1394L40BE,518 功能描述:視頻 IC 1394 A/V LINK LAYER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
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