參數(shù)資料
型號: PDI1394L21BE
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 1394 full duplex AV link layer controller
中文描述: 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, SOT-407-1, LQFP-100
文件頁數(shù): 14/42頁
文件大小: 233K
代理商: PDI1394L21BE
Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
14
13.0
THERMAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITION
LIMITS
UNIT
MIN
TYP
68
MAX
R
Θ
jA
Junction-to-free-air thermal resistance
Board mounted, no air flow
°
C/W
14.0
AC CHARACTERISTICS
SYMBOL
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Transmit jitter
TPA, TPB
0.15
ns
Transmit skew
Between TPA and TPB
0.10
ns
t
r
t
f
TPA, TPB differential output voltage rise time
10% to 90%; At 1394 connector
0.5
1.2
ns
TPA, TPB differential output voltage fall time
90% to 10%; At 1394 connector
0.5
1.2
ns
t
SU
t
H
t
D
Setup time, CTL0, CTL1, D0–D7, LREQ to SYSCLK
50% to 50%; See Figure 2
5
ns
Hold time, CTL0, CTL1, D0–D7, LREQ after SYSCLK
50% to 50%; See Figure 2
0
ns
Delay time SYSCLK to CTL0, CTL1, D0–D7
50% to 50%; See Figure 3
0.5
11
ns
C
L
Capacitance load value CTL0, CTL1, D0–D7,
SYSCLK
Input capacitance CTL0, CTL1, D0–D7, LREQ
10
pF
C
i
3.3
pF
15.0
TIMING WAVEFORMS
SV01098
56
TPAn+
TPBn+
TPAn–
TPBn–
Figure 1.
Test load diagram
SV01099
t
SU
t
H
SYSCLK
Dn, CTLn, LREQ
Figure 2.
Dn, CTLn, LREQ input setup and hold times
SV01803
t
D
SYSCLK
Dn, CTLn
Figure 3.
Dn, CTLn, output delay relative to SYSCLK
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