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參數(shù)資料
| 型號： | PDI1394L21BE |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1394 full duplex AV link layer controller |
| 中文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, SOT-407-1, LQFP-100 |
| 文件頁數(shù)： | 26/42頁 |
| 文件大?。?/td> | 233K |
| 代理商： | PDI1394L21BE |
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Philips Semiconductors
Preliminary data
PDI1394P23
2-port/1-port 400 Mbps physical layer interface
2001 Sep 06
26
18.0
The PDI1394P23 is designed to operate with an LLC such as the
Philips Semiconductors PDI1394L21, PDI1394L40, or PDI1394L41.
The following paragraphs describe the operation of the PHY-LLC
interface.
PRINCIPLES OF OPERATION
The interface to the LLC consists of the SYSCLK, CTL0–CTL1,
D0–D7, LREQ, LPS, C/LKON, and ISO terminals on the
PDI1394P23 as shown in Figure 13.
LINK LAYER
CONTROLLER
PDI1394P23
SYSCLK
CTL0–CTL1
D0–D7
LREQ
LPS
C/LKON
/ISO
/ISO
/ISO
SV01822
Figure 13.
PHY-LLC interface
The SYSCLK terminal provides a 49.152 MHz interface clock to
which all control and data signals are synchronized. These signals
are sampled on the rising edge of SYSCLK.
The CTL0 and CTL1 terminals form a bidirectional control bus,
which controls the flow of information and data between the
PDI1394P23 and LLC.
The D0–D7 terminals form a bidirectional data bus, which is used to
transfer status information, control information, or packet data
between the devices. The PDI1394P23 supports S100, S200, and
S400 data transfers over the D0–D7 data bus. In S100 operation
only the D0 and D1 terminals are used; in S200 operation only the
D0–D3 terminals are used; and in S400 operation all D0–D7
terminals are used for data transfer. When the PDI1394P23 is in
control of the D0–D7 bus, unused Dn terminals are driven low during
S100 and S200 operations. When the LLC is in control of the D0–D7
bus, unused Dn terminals are ignored by the PDI1394P23.
The LREQ terminal is controlled by the LLC to send serial service
requests to the PHY in order to request access to the serial bus for
packet transmission, read or write PHY registers, or control
arbitration acceleration.
The LPS and C/LKON terminals are used for power management of
the PHY and LLC. The LPS terminal indicates the power status of
the LLC, and may be used to reset the PHY-LLC interface or to
disable SYSCLK. The C/LKON terminal is used to send a wake-up
notification to the LLC and to indicate an interrupt to the LLC when
either LPS is inactive or the PHY register L bit is zero.
The ISO terminal is used to enable the output differentiation logic on
the CTL0–CTL1 and D0–D7 terminals. Output differentiation is
required when an isolation barrier of the type described in Annex J
of IEEE Std 1394-1995 is implemented between the PHY and LLC.
The PDI1394P23 normally controls the CTL0–CTL1 and D0–D7
bidirectional buses. The LLC is allowed to drive these buses only
after the LLC has been granted permission to do so by the PHY.
There are four operations that may occur on the PHY-LLC interface:
link service request, status transfer, data transmit, and data receive.
The LLC issues a service request to read or write a PHY register, to
request the PHY to gain control of the serial bus in order to transmit
a packet, or to control arbitration acceleration.
The PHY may initiate a status transfer either autonomously or in
response to a register read request from the LLC.
The PHY initiates a receive operation whenever a packet is received
from the serial bus.
The PHY initiates a transmit operation after winning control of the
serial-bus following a bus request by the LLC. The transmit
operation is initiated when the PHY grants control of the interface to
the LLC.
The encoding of the CTL0–CTL1 bus is shown in Table 9 and
Table 10.
Table 9. CTL encoding when PHY has control of the bus
CTL0
CTL1
NAME
DESCRIPTION
0
0
Idle
No activity (this is the default mode)
0
1
Status
Status information is being sent from the PHY to the LLC
1
0
Receive
An incoming packet is being sent from the PHY to the LLC
1
1
Grant
The LLC has been given control of the bus to send an outgoing packet
Table 10. CTL encoding when LLC has control of the bus
CTL0
CTL1
NAME
DESCRIPTION
0
0
Idle
The LLC releases the bus (transmission has been completed)
0
1
Hold
The LLC is holding the bus while data is being prepared for transmission, or indicating
that another packet is to be transmitted (concatenated) without arbitrating
An outgoing packet is being sent from the LLC to the PHY
1
0
Transmit
1
1
Reserved
None
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PDI1394L21BP | 1394 full duplex AV link layer controller |
| PDL-TTL-7-1 | Programmable Delay Line |
| PDL-TTL-7-14 | Programmable Delay Line |
| PDL-TTL-7-15 | Programmable Delay Line |
| PDL-TTL-7-2 | Programmable Delay Line |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PDI1394L21BP | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 full duplex AV link layer controller |
| PDI1394L40 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:1394 enhanced AV link layer controller |
| PDI1394L40BE | 制造商:NXP Semiconductors 功能描述:1 CHANNEL(S), 400M BPS, SERIAL COMM CONTROLLER, PQFP144 |
| PDI1394L40BE,518 | 功能描述:視頻 IC 1394 A/V LINK LAYER RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| PDI1394L40BE,551 | 制造商:NXP Semiconductors 功能描述:1394 A/V LINK LAYER - Trays |
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