參數(shù)資料
型號(hào): PCM1792A
英文描述: 24-bit,192-khz sampling,advanced segment, audio stereo digital-to-analog converter
中文描述: 24位,192 - kHz的采樣,先進(jìn)的部分,立體聲音頻數(shù)字模擬轉(zhuǎn)換器
文件頁(yè)數(shù): 15/59頁(yè)
文件大?。?/td> 500K
代理商: PCM1792A
SLES105B FEBRUARY 2004 REVISED NOVEMBER 2006
www.ti.com
15
SYSTEM CLOCK AND RESET FUNCTIONS
System Clock Input
The PCM1792A requires a system clock for operating the digital interpolation filters and advanced segment DAC
modulators. The system clock is applied at the SCK input (pin 7). The PCM1792A has a system clock detection circuit that
automatically senses if the system clock is operating between 128 f
S
and
768 f
S
. Table 1 shows examples of system clock
frequencies for common audio sampling rates. If the oversampling rate of the delta-sigma modulator is selected as 128 f
S
,
the system clock frequency is over 256 f
S
.
Figure 24 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock
source with low phase jitter and noise. One of the Texas Instruments’ PLL1700 family of multiclock generators is an
excellent choice for providing the PCM1792A system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY
SYSTEM CLOCK FREQUENCY (fSCK) (MHz)
256 fS
6.144(1)
8.192
128 fS
4.096(1)
5.6488(1)
6.144(1)
192 fS
384 fS
12.288
512 fS
16.384
768 fS
24.576
32 kHz
44.1 kHz
8.4672
11.2896
16.9344
22.5792
33.8688
48 kHz
9.216
12.288
18.432
24.576
49.152(1)
(2)
36.864
73.728(1)
(2)
96 kHz
12.288
18.432
24.576
49.152(1)
36.864
73.728(1)
192 kHz
24.576
36.864
(1)This system clock rate is not supported in I2C fast mode.
(2)This system clock rate is not supported for the given sampling frequency.
t(SCKH)
t(SCY)
System Clock (SCK)
t(SCKL)
2 V
0.8 V
H
L
PARAMETERS
MIN
MAX
UNITS
t(SCY)
t(SCKH)
t(SCKL)
System clock pulse cycle time
13
ns
System clock pulse duration, HIGH
0.4 (SCY)
0.4 (SCY)
ns
System clock pulse duration, LOW
ns
Figure 24. System Clock Input Timing
Power-On and External Reset Functions
The PCM1792A includes a power-on reset function. Figure 25 shows the operation of this function. With V
DD
> 2 V, the
power-on reset function is enabled. The initialization sequence requires 1024 system clocks from the time V
DD
> 2 V. After
the initialization period, the PCM1792A is set to its default reset state, as described in the
MODE CONTROL REGISTERS
section of this data sheet.
The PCM1792A also includes an external reset capability using the RST input (pin 14). This allows an external controller
or master reset circuit to force the PCM1792A to initialize to its default reset state.
Figure 26 shows the external reset operation and timing. The RST pin is set to logic 0 for a minimum of 20 ns. The RST
pin is then set to a logic 1 state, thus starting the initialization sequence, which requires 1024 system clock periods. The
external reset is especially useful in applications where there is a delay between the PCM1792A power up and system clock
activation.
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PCM1792ADBRG4 功能描述:音頻數(shù)/模轉(zhuǎn)換器 IC 24B 192kHz Sampling Adv Seg Aud St DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量: 分辨率:16 bit 接口類(lèi)型:I2S, UBS 轉(zhuǎn)換速率: 信噪比:98 dB 工作電源電壓:5 V DAC 輸出端數(shù)量:2 工作溫度范圍:- 25 C to + 85 C 電源電流:23 mA 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-32 封裝:Reel