參數(shù)資料
型號: PCF85176T
廠商: NXP SEMICONDUCTORS
元件分類: 顯示驅(qū)動器
英文描述: Universal LCD driver for low multiplex rates
中文描述: LIQUID CRYSTAL DISPLAY DRIVER, PDSO56
封裝: 6.10 MM, PLASTIC, MO-153, SOT364-1, TSSOP-56
文件頁數(shù): 26/47頁
文件大?。?/td> 405K
代理商: PCF85176T
PCF85176
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 27 June 2011
26 of 47
NXP Semiconductors
PCF85176
Universal LCD driver for low multiplex rates
8.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte.
A master receiver must generate an acknowledge after the reception of each byte that
has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I
2
C-bus is illustrated in
Figure 17
.
Fig 16. System configuration
mga807
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
Fig 17. Acknowledgement of the I
2
C-bus
mbc602
S
START
condition
9
8
2
1
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from
master
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