參數(shù)資料
型號(hào): PCA9509
廠商: NXP Semiconductors N.V.
英文描述: Level translating I2C-bus/SMBus repeater
中文描述: 級(jí)別翻譯I2C-bus/SMBus中繼器
文件頁(yè)數(shù): 5/16頁(yè)
文件大?。?/td> 92K
代理商: PCA9509
PCA9509_1
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 01 — 27 June 2006
5 of 16
Philips Semiconductors
PCA9509
Level translating I
2
C-bus/SMBus repeater
7.
Application design-in information
A typical application is shown in
Figure 4
. In this example, the CPU is running on a 1.1 V
I
2
C-bus while the master is connected to a 3.3 V bus. Both buses run at 400 kHz. Master
devices can be placed on either bus.
When port B of the PCA9509 is pulled LOW by a driver on the I
2
C-bus, a CMOS
hysteresis detects the falling edge when it goes below 0.3V
CC(B)
and causes the internal
driver on port A to turn on, causing port A to pull down to about 0.2 V. When port A of the
PCA9509 falls, first a comparator detects the falling edge and causes the internal driver
on port B to turn on and pull the port B pin down to ground. In order to illustrate what
would be seen in a typical application, refer to
Figure 5
and
Figure 6
. If the bus master in
Figure 4
were to write to the slave through the PCA9509, waveforms shown in
Figure 5
would be observed on the B bus. This looks like a normal I
2
C-bus transmission.
On the A bus side of the PCA9509, the clock and data lines would have a positive offset
from ground equal to the V
OL
of the PCA9509. After the 8
th
clock pulse, the data line will
be pulled to the V
OL
of the master device, which is very close to ground in this example. At
the end of the acknowledge, the level rises only to the LOW level set by the driver in the
PCA9509 for a short delay while the B bus side rises above 0.5V
CC(B)
, then it continues
HIGH. It is important to note that any arbitration or clock stretching events require that the
LOW level on the A bus side at the input of the PCA9509 (V
IL
) is below V
ILc
to be
recognized by the PCA9509 and then transmitted to the B bus side.
Fig 4.
Typical application
Fig 5.
Bus B SMBus/I
2
C-bus waveform
002aac128
V
CC(B)
V
CC(A)
PCA9509
A1
B1
A2
B2
EN
10 k
10 k
SDA
SCL
MASTER
CPU
SLAVE
400 kHz
SDA
SCL
bus A
bus B
3.3 V
1.1 V
10 k
1.1 V
002aab644
9th clock pulse
acknowledge
SCL
SDA
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