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參數(shù)資料
| 型號(hào)： | PC745BVZFU400LD |
| 英文描述： | MICROPROCESSOR|32-BIT|CMOS|BGA|255PIN|PLASTIC |
| 中文描述： | 微處理器| 32位|的CMOS | BGA封裝| 255PIN |塑料 |
| 文件頁數(shù)： | 14/48頁 |
| 文件大?。?/td> | 276K |
| 代理商： | PC745BVZFU400LD |
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PC755B/745B
Table 2. Pinout Listing for the PC755B, 360 PBGA Package
Signal Name
Notes
3.3V
1.8V/2.0V
I/O
Active
Pin Number
TDI
B7
High
Input
—
—
6
TDO
D9
High
Output
—
—
TEA
J1
Low
Input
—
—
TLBISYNC
A3
Low
Input
—
—
TMS
C8
High
Input
—
—
6
TRST
A10
Low
Input
—
—
6
TS
K7
Low
I/O
—
—
TSIZ[0–2]
A9, B9, C9
High
Output
—
—
TT[0–4]
C10, D11, B12, C12, F11
High
I/O
—
—
WT
C3
Low
Output
—
—
VDD
G8, G10, G12, J8, J10, J12, L8, L10,
L12, N8, N10, N12
—
—
2.0V
2.0V
VOLTDET
K13
High
Output
—
—
7
Notes:
1. OVdd supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE,
and L2ZZ); L2OVDD supplies power to the L2 cache interface (L2ADDR[0-16], L2DATA[0-63], L2DP[0-7] and
L2SYNC-OUT) and the L2 control signals; and Vdd supplies power to the processor core and the PLL and DLL (after
filtering to become AVDD and L2AVDD respectively). These columns serve as a reference for the nominal voltage sup-
ported on a given signal as selected by the BVSEL/L2VSEL pin configurations of Table 4 and the voltage supplied. For
actual recommended value of Vin or supply voltages see Table 5.
2. These are test signals for factory use only and must be pulled up to OVdd for normal machine operation.
3. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either
OVDD (selects 3.3V) or to OGND (selects 1.8V/2.0V).
4. These pins are reserved for potential future use as additional L2 address pins.
5. Uses one of 9 existing no-connects in PC750’s 360-bga package.
6. Internal pull up on die.
7. Internally tied to L2OVDD in the PC755B 360-bga package to indicate the power present at the L2 cache interface. This
signal is not a power supply input.
Caution:
This is different from the PC745B 255-bga package.
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