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參數(shù)資料
| 型號： | PC33887VW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 運動控制電子 |
| 英文描述： | STEPPER MOTOR CONTROLLER, PDSO20 |
| 封裝： | LEAD FREE, PLASTIC, HSOP-20 |
| 文件頁數(shù)： | 27/32頁 |
| 文件大小： | 859K |
| 代理商： | PC33887VW |
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Analog Integrated Circuit Device Data
4
Freescale Semiconductor
33887
TERMINAL CONNECTIONS
Figure 4. 33887 Terminal Connections
Table 2. PQFN TERMINAL DEFINITIONS
A functional description of each terminal can be found in the Functional Terminal Description section, page 20.
Terminal
Name
Formal Name
Definition
1, 7, 10, 16,
19, 28, 31
NC
No Connect
No internal connection to this terminal.
2
D1
Disable 1
Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.
3
IN2
Logic Input Control 2
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
4
EN
Enable
Logic input Enable control of device (i.e., EN logic HIGH = full operation,
EN logic LOW = Sleep Mode).
5, 6, 12, 13, 34, 35
V+
Positive Power Supply
Positive supply connections.
8
AGND
Analog Ground
Low-current analog signal ground.
9
FS
Fault Status for H-Bridge
Open drain active LOW Fault Status output requiring a pull-up resistor to
5.0 V.
11
IN1
Logic Input Control 1
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
14, 15, 17, 18
OUT1
H-Bridge Output 1
Output 1 of H-Bridge.
20
FB
Feedback for H-Bridge
Current feedback output providing ground referenced 1/375th ratio of
H-Bridge high-side current.
21–26
PGND
Power Ground
High-current power ground.
27
D2
Disable 2
Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When D2 is Logic LOW, both outputs are tri-stated.
29, 30, 32, 33
OUT2
H-Bridge Output 2
Output 2 of H-Bridge.
36
CCP
Charge Pump Capacitor
External reservoir capacitor connection for internal charge pump
capacitor.
Pad
Thermal
Interface
Exposed Pad Thermal
Interface
Exposed pad thermal interface for sinking heat from the device.
Note: Must be DC-coupled to analog ground and power ground via very
low impedance path to prevent injection of spurious signals into IC
substrate.
D2
NC
28
27
26
25
24
23
22
21
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
PGND
IN2
D1
EN
V+
NC
AGND
FS
V+
CCP
V+
OUT
2
OUT
2
NC
OUT
2
OUT
2
V+
IN
1
V+
OUT1
NC
OUT1
20
FB
19
NC
10
NC
1
NC
Transparent Top View of Package
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