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參數(shù)資料
| 型號(hào)： | PC33887VW |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | STEPPER MOTOR CONTROLLER, PDSO20 |
| 封裝： | LEAD FREE, PLASTIC, HSOP-20 |
| 文件頁(yè)數(shù)： | 23/32頁(yè) |
| 文件大小： | 859K |
| 代理商： | PC33887VW |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
3
33887
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
Figure 3. 33887 Terminal Connections
Table 1. 33887 HSOP TERMINAL DEFINITIONS
A functional description of each terminal can be found in the Functional Terminal Description section, page 20.
Terminal
Name
Formal Name
Definition
1
AGND
Analog Ground
Low-current analog signal ground.
2
FS
Fault Status for H-Bridge
Open drain active LOW Fault Status output requiring a pull-up resistor to
5.0 V.
3
IN1
Logic Input Control 1
Logic input control of OUT1 (i.e., IN1 logic HIGH = OUT1 HIGH).
4, 5, 16
V+
Positive Power Supply
Positive supply connections
6, 7
OUT1
H-Bridge Output 1
Output 1 of H-Bridge.
8
FB
Feedback for H-Bridge
Current sensing feedback output providing ground referenced 1/375th
(0.00266) of H-Bridge high-side current.
9–12
PGND
Power Ground
High-current power ground.
13
D2
Disable 2
Active LOW input used to simultaneously tri-state disable both H-Bridge
outputs. When D2 is Logic LOW, both outputs are tri-stated.
14, 15
OUT2
H-Bridge Output 2
Output 2 of H-Bridge.
17
CCP
Charge Pump Capacitor
External reservoir capacitor connection for internal charge pump capacitor.
18
D1
Disable 1
Active HIGH input used to simultaneously tri-state disable both H-Bridge
outputs. When D1 is Logic HIGH, both outputs are tri-stated.
19
IN2
Logic Input Control 2
Logic input control of OUT2 (i.e., IN2 logic HIGH = OUT2 HIGH).
20
EN
Enable
Logic input Enable control of device (i.e., EN logic HIGH = full operation, EN
logic LOW = Sleep Mode).
Tab/Pad
Thermal
Interface
Exposed Pad Thermal
Interface
Exposed pad thermal interface for sinking heat from the device.
Note Must be DC-coupled to analog ground and power ground via very low
impedance path to prevent injection of spurious signals into IC substrate.
EN
AGND
IN2
D1
CCP
V+
OUT2
D2
PGND
FS
V+
OUT1
FB
PGND
IN1
V+
1
2
3
4
5
6
7
8
9
10
20
19
16
15
14
13
12
11
18
17
Tab
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