參數(shù)資料
型號(hào)： PC28F640J3A-115
廠商： Intel Corp.
英文描述： Intel StrataFlash Memory (J3)
中文描述： 英特爾StrataFlash存儲(chǔ)器（J3）
文件頁(yè)數(shù)： 58/72頁(yè)
文件大小： 905K
代理商： PC28F640J3A-115
256-Mbit J3 (x8/x16)
58
Datasheet
Table 31. Protection Register Information
Offset
(1)
P = 31h
Length
Description
(Optional Flash Features and Commands)
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection bytes are available
Protection Field 1: Protection Description
This field describes user-available One Time Programmable
(OTP) Protection Register bytes. Some are pre-programmed
with device-unique serial numbers. Others are user-
programmable. Bits 0-15 point to the Protection Register lock
byte, the section’s first byte. The following bytes are factory
pre-programmed and user-programmable.
bits 0-7 = Lock/bytes JEDEC-plane physical low address
bits 8-15 = Lock/bytes JEDEC-plane physical high address
bits 16-23 = “n” such that 2
= factory pre-programmed bytes
bits 24-31 = “n” such that 2
n
= user-programmable bytes
Add.
Hex
Code
Value
(P+E)h
1
3F:
--01
01
(P+F)h
(P+10)h
(P+11)h
(P+12)h
4
40:
41:
42:
43:
--80
--00
--03
--03
80h
00h
8bytes
8bytes
NOTE:
1. The variable P is a pointer which is defined at CFI offset 15h.
Table 32. Burst Read Information
Offset
(1)
P = 31h
Length
Description
(Optional Flash Features and Commands)
Page Mode Read capability
bits 0–7 = “n” such that 2
n
HEX value represents the number
of read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read page buffer.
Number of synchronous mode read configuration fields that
follow. 00h indicates no burst capability.
Reserved for future use
Add.
Hex
Code
Value
(P+13)h
1
44:
--03
8 byte
(P+14)h
1
45:
--00
0
(P+15)h
NOTE:
1. The variable P is a pointer which is defined at CFI offset 15h.
46:
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