參數(shù)資料
型號(hào)： PC28F640J3A-115
廠商： Intel Corp.
英文描述： Intel StrataFlash Memory (J3)
中文描述： 英特爾StrataFlash存儲(chǔ)器（J3）
文件頁(yè)數(shù)： 29/72頁(yè)
文件大?。?/td> 905K
代理商： PC28F640J3A-115
256-Mbit J3 (x8/x16)
Datasheet
29
7.4
Reset Operation
NOTE:
STS is shown in its default mode (RY/BY#).
7.5
AC Test Conditions
NOTE:
AC test inputs are driven at V
for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and
output timing ends, at V
CCQ
/2 V (50% of V
CCQ
). Input rise and fall times (10% to 90%) < 5 ns.
Figure 14. AC Waveform for Reset Operation
V
IH
V
IL
P1
V
IL
V
IH
P2
RP# (P)
STS (R)
Table 11. Reset Specifications
#
Sym
Parameter
Min
Max
Unit
Notes
P1
t
PLPH
RP# Pulse Low Time
(If RP# is tied to V
CC
, this specification is not
applicable)
35
μs
1,2
P2
t
PHRH
RP# High to Reset during Block Erase, Program, or
Lock-Bit Configuration
100
ns
1,3
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not
executing then the minimum required RP# Pulse Low Time is 100 ns.
3. A reset time, t
, is required from the latter of STS (in RY/BY# mode) or RP# going high until
outputs are valid.
Figure 15. Transient Input/Output Reference Waveform for V
CCQ
= 2.7 V–3.6 V
Output
Test Points
Input V
CCQ
/2
0.0
V
CCQ
V
CCQ
/2
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